SN74LV08A-Q1 Positive-AND Gates Datasheet

SN74LV08A-Q1 Datasheet, PDF, Equivalent


Part Number

SN74LV08A-Q1

Description

Quadruple 2-Input Positive-AND Gates

Manufacture

etcTI

Total Page 12 Pages
Datasheet
Download SN74LV08A-Q1 Datasheet


SN74LV08A-Q1
SN74LV08A-Q1
QUADRUPLE 2-INPUT POSITIVE-AND GATE
D Qualified for Automotive Applications
D Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
D Typical VOHV (Output VOH Undershoot)
>2.3 V at VCC = 3.3 V, TA = 25°C
D Supports Mixed-Mode Voltage Operation on
All Ports
D Ioff Supports Partial-Power-Down Mode
Operation
D Latch-Up Performance Exceeds 250 mA Per
JESD 17
D ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
SCLS465C − FEBRUARY 2003 − REVISED JANUARY 2008
PW PACKAGE
(TOP VIEW)
1A
1B
1Y
2A
2B
2Y
GND
1
2
3
4
5
6
7
14 VCC
13 4B
12 4A
11 4Y
10 3B
9 3A
8 3Y
description/ordering information
This quadruple 2-input positive-AND gate is designed for 2-V to 5.5-V VCC operation.
The SN74LV08A performs the Boolean function Y + A B or Y + A ) B in positive logic.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
−40°C to 105°C TSSOP − PW Tape and reel SN74LV08ATPWRQ1 LV08ATQ
For the most current package and ordering information, see the Package Option Addendum at the end
of this document, or see the TI web site at http://www.ti.com.
Package drawings, thermal data, and symbolization are available at http://www.ti.com/packaging.
FUNCTION TABLE
(each gate)
INPUTS
AB
OUTPUT
Y
HH
H
LX
L
XL
L
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 2008, Texas Instruments Incorporated
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
1

SN74LV08A-Q1
SN74LV08A-Q1
QUADRUPLE 2-INPUT POSITIVE-AND GATE
SCLS465C − FEBRUARY 2003 − REVISED JANUARY 2008
logic diagram, each gate (positive logic)
A
B
Y
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Voltage range applied to any output in the high-impedance
or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Package thermal impedance, θJA (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 5.5 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
2 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443


Features SN74LV08A-Q1 QUADRUPLE 2-INPUT POSITIVE- AND GATE D Qualified for Automotive Ap plications D Typical VOLP (Output Groun d Bounce) <0.8 V at VCC = 3.3 V, TA = 2 5°C D Typical VOHV (Output VOH Undersh oot) >2.3 V at VCC = 3.3 V, TA = 25°C D Supports Mixed-Mode Voltage Operation on All Ports D Ioff Supports Partial-P ower-Down Mode Operation D Latch-Up Per formance Exceeds 250 mA Per JESD 17 D E SD Protection Exceeds JESD 22 − 2000- V Human-Body Model (A114-A) − 200-V M achine Model (A115-A) − 1000-V Charge d-Device Model (C101) SCLS465C − FEB RUARY 2003 − REVISED JANUARY 2008 PW PACKAGE (TOP VIEW) 1A 1B 1Y 2A 2B 2Y G ND 1 2 3 4 5 6 7 14 VCC 13 4B 12 4A 1 1 4Y 10 3B 9 3A 8 3Y description/order ing information This quadruple 2-input positive-AND gate is designed for 2-V t o 5.5-V VCC operation. The SN74LV08A pe rforms the Boolean function Y + A • B or Y + A ) B in positive logic. This d evice is fully specified for partial-po wer-down applications using Ioff. The Ioff circuitry disables the outputs, pr.
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