SN74LV11A POSITIVE-AND GATES Datasheet

SN74LV11A Datasheet, PDF, Equivalent


Part Number

SN74LV11A

Description

TRIPLE 3-INPUT POSITIVE-AND GATES

Manufacture

etcTI

Total Page 17 Pages
Datasheet
Download SN74LV11A Datasheet


SN74LV11A
SN54LV11A, SN74LV11A
TRIPLE 3ĆINPUT POSITIVEĆAND GATES
D 2-V to 5.5-V VCC Operation
D Max tpd of 7 ns at 5 V
D Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
D Typical VOHV (Output VOH Undershoot)
>2.3 V at VCC = 3.3 V, TA = 25°C
D Support Mixed-Mode Voltage Operation on
All Ports
D Ioff Supports Partial-Power-Down Mode
Operation
D Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
D ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
description/ordering information
These triple 3-input positive-AND gates are
designed for 2-V to 5.5-V VCC operation.
The ’LV11A devices perform the Boolean function
Y + A B C or Y + A ) B ) C in positive
logic.
These devices are fully specified for
partial-power-down applications using Ioff. The Ioff
circuitry disables the outputs, preventing
damaging current backflow through the devices
when they are powered down.
SCES345D − DECEMBER 2000 − REVISED APRIL 2005
SN54LV11A . . . J OR W PACKAGE
SN74LV11A . . . D, DB, DGV, NS, OR PW PACKAGE
(TOP VIEW)
1A
1B
2A
2B
2C
2Y
GND
1
2
3
4
5
6
7
14 VCC
13 1C
12 1Y
11 3C
10 3B
9 3A
8 3Y
SN54LV11A . . . FK PACKAGE
(TOP VIEW)
2A
3 2 1 20 19
4 18
1Y
NC 5
17 NC
2B 6
16 3C
NC 7
15 NC
2C 8
14 3B
9 10 11 12 13
NC − No internal connection
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
SOIC − D
Tube of 50
Reel of 2500
SN74LV11AD
SN74LV11ADR
LV11A
SOP − NS
Reel of 2000 SN74LV11ANSR
74LV11A
−40°C to 85°C
SSOP − DB
Reel of 2000
Tube of 90
SN74LV11ADBR
SN74LV11APW
LV11A
TSSOP − PW
Reel of 2000
Reel of 250
SN74LV11APWR
SN74LV11APWT
LV11A
TVSOP − DGV Reel of 2000 SN74LV11ADGVR
LV11A
CDIP − J
Tube of 25
SNJ54LV11AJ
SNJ54LV11AJ
−55°C to 125°C CFP − W
Tube of 150
SNJ54LV11AW
SNJ54LV11AW
LCCC − FK
Tube of 55
SNJ54LV11AFK
SNJ54LV11AFK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright 2005, Texas Instruments Incorporated
1

SN74LV11A
SN54LV11A, SN74LV11A
TRIPLE 3ĆINPUT POSITIVEĆAND GATES
SCES345D − DECEMBER 2000 − REVISED APRIL 2005
FUNCTION TABLE
(each gate)
INPUTS
ABC
OUTPUT
Y
HHH
H
LXX
L
XLX
L
XXL
L
logic diagram, each gate (positive logic)
A
B
C
Y
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Output voltage range applied in high or low state, VO (see Notes 1 and 2) . . . . . . . . . . −0.5 V to VCC + 0.5 V
Voltage range applied to any output in the power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Package thermal impedance, θJA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 5.5 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
2 POST OFFICE BOX 655303 DALLAS, TEXAS 75265


Features SN54LV11A, SN74LV11A TRIPLE 3ĆINPUT POS ITIVEĆAND GATES D 2-V to 5.5-V VCC Op eration D Max tpd of 7 ns at 5 V D Typi cal VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C D Typical VO HV (Output VOH Undershoot) >2.3 V at VC C = 3.3 V, TA = 25°C D Support Mixed-M ode Voltage Operation on All Ports D Io ff Supports Partial-Power-Down Mode Ope ration D Latch-Up Performance Exceeds 1 00 mA Per JESD 78, Class II D ESD Prote ction Exceeds JESD 22 − 2000-V Human- Body Model (A114-A) − 200-V Machine M odel (A115-A) − 1000-V Charged-Device Model (C101) description/ordering info rmation These triple 3-input positive-A ND gates are designed for 2-V to 5.5-V VCC operation. The ’LV11A devices per form the Boolean function Y + A • B C or Y + A ) B ) C in positive logic . These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the o utputs, preventing damaging current bac kflow through the devices when they are powered down. SCES345D − DECEMBER 2000.
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