SN74LV11A-EP POSITIVE-AND GATES Datasheet

SN74LV11A-EP Datasheet, PDF, Equivalent


Part Number

SN74LV11A-EP

Description

TRIPLE 3-INPUT POSITIVE-AND GATES

Manufacture

etcTI

Total Page 12 Pages
Datasheet
Download SN74LV11A-EP Datasheet


SN74LV11A-EP
SN74LV11AĆEP
TRIPLE 3ĆINPUT POSITIVEĆAND GATE
D Controlled Baseline
− One Assembly/Test Site, One Fabrication
Site
D Extended Temperature Performance of
−40°C to 105°C
D Enhanced Diminishing Manufacturing
Sources (DMS) Support
D Enhanced Product-Change Notification
D Qualification Pedigree
D 2-V to 5.5-V VCC Operation
Component qualification in accordance with JEDEC and industry
standards to ensure reliable operation over an extended
temperature range. This includes, but is not limited to, Highly
Accelerated Stress Test (HAST) or biased 85/85, temperature
cycle, autoclave or unbiased HAST, electromigration, bond
intermetallic life, and mold compound life. Such qualification
testing should not be viewed as justifying use of this component
beyond specified performance and environmental limits.
SCLS564A − JANUARY 2004 − REVISED MAY 2004
D Typical VOLP (Output Ground Bounce)
<0.8 V at VCC= 3.3 V, TA = 25°C
D Typical VOHV (Output VOH Undershoot)
>2.3 V at VCC = 3.3 V, TA = 25°C
D Supports Mixed-Mode Voltage Operation on
All Ports
D Ioff Supports Partial-Power-Down Mode
Operation
PW PACKAGE
(TOP VIEW)
1A
1B
2A
2B
2C
2Y
GND
1
2
3
4
5
6
7
14 VCC
13 1C
12 1Y
11 3C
10 3B
9 3A
8 3Y
description/ordering information
This triple 3-input positive-AND gate is designed for 2-V to 5.5-V VCC operation.
The SN74LV11A performs the Boolean function Y + A B C or Y + A ) B ) C in positive logic.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
TA
PACKAGE‡
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
−40°C to 105°C TSSOP − PW Tape and reel SN74LV11ATPWREP LV11AEP
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
FUNCTION TABLE
(each gate)
INPUTS
ABC
OUTPUT
Y
HHH
H
LXX
L
XLX
L
XXL
L
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright 2004, Texas Instruments Incorporated
1

SN74LV11A-EP
SN74LV11AĆEP
TRIPLE 3ĆINPUT POSITIVEĆAND GATE
SCLS564A − JANUARY 2004 − REVISED MAY 2004
logic diagram, each gate (positive logic)
A
B
C
Y
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Output voltage range applied in high or low state, VO (see Notes 1 and 2) . . . . . . . . . . −0.5 V to VCC + 0.5 V
Voltage range applied to any output in the power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Package thermal impedance, θJA (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 5.5 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
2 POST OFFICE BOX 655303 DALLAS, TEXAS 75265


Features SN74LV11AĆEP TRIPLE 3ĆINPUT POSITIVEĆ AND GATE D Controlled Baseline − One Assembly/Test Site, One Fabrication Si te D Extended Temperature Performance o f −40°C to 105°C D Enhanced Diminis hing Manufacturing Sources (DMS) Suppor t D Enhanced Product-Change Notificatio n D Qualification Pedigree† D 2-V to 5.5-V VCC Operation † Component quali fication in accordance with JEDEC and i ndustry standards to ensure reliable op eration over an extended temperature ra nge. This includes, but is not limited to, Highly Accelerated Stress Test (HAS T) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigr ation, bond intermetallic life, and mol d compound life. Such qualification tes ting should not be viewed as justifying use of this component beyond specified performance and environmental limits. SCLS564A − JANUARY 2004 − REVISED MAY 2004 D Typical VOLP (Output Ground Bounce) <0.8 V at VCC= 3.3 V, TA = 25° C D Typical VOHV (Output VOH Undershoot) >2.3 V at VCC = 3.3 V, TA = 25°C D Suppo.
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