SN74LV11A-EP

SN74LV11AĆEP TRIPLE 3ĆINPUT POSITIVEĆAND GATE D Controlled Baseline − One Assembly/Test Site, One Fabrication Site D Extended Temperature Performance of −40°C to 105°C D Enhanced Diminishing Manufacturing Sources (DMS) Support D Enhanced Product-Change Notification D Qualification Pedigree† D 2-V to 5.5-V VCC Operation † Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits. SCLS564A − JANUARY 2004 − REVISED MAY 2004 D Typical VOLP (Output Ground Bounce) <0.8 V at VCC= 3.3 V, TA = 25°C D Typical VOHV (Output VOH Undershoot) >2.3 V at VCC = 3.3 V, TA = 25°C D Supports Mixed-Mode Voltage Operation on All Ports D Ioff Supports Partial-Power-Down Mode Operation PW PACKAGE (TOP VIEW) 1A 1B 2A 2B 2C 2Y GND 1 2 3 4 5 6 7 14 VCC 13 1C 12 1Y 11 3C 10 3B 9 3A 8 3Y description/ordering information This triple 3-input positive-AND gate is designed for 2-V to 5.5-V VCC operation. The SN74LV11A performs the Boolean function Y + A B C or Y + A ) B ) C in positive logic. This device is fully specified for partial-power-down applications using Ioff. The Ioff cir...