Document
SN74LV123AĆEP DUAL RETRIGGERABLE MONOSTABLE MULTIVIBRATOR
WITH SCHMITTĆTRIGGER INPUTS SCLS498A − MAY 2003 − REVISED MAY 2004
D Controlled Baseline
− One Assembly/Test Site, One Fabrication Site
D Extended Temperature Performance of
−40°C to 105°C
D Enhanced Diminishing Manufacturing
Sources (DMS) Support
D Enhanced Product-Change Notification D Qualification Pedigree† D Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
D Typical VOHV (Output VOH Undershoot)
>2.3 V at VCC = 3.3 V, TA = 25°C
D Supports Mixed-Mode Voltage Operation on
All Ports
D Schmitt-Trigger Circuitry on A, B, and CLR
Inputs for Slow Input Transition Rates
† Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.
description/ordering information
D Edge Triggered From Active-High or
Active-Low Gated Logic Inputs
D Ioff Supports Partial-Power-Down Mode
Operation
D Retriggerable for Very Long Output Pulses,
Up To 100% Duty Cycle
D Overriding Clear Terminates Output Pulse D Glitch-Free Power-Up Reset on Outputs D ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A) − 200-V Machine Model (A115-A) − 1000-V Charged-Device Model (C101)
PW PACKAGE (TOP VIEW)
1A 1B 1CLR 1Q 2Q 2Cext 2Rext/Cext GND
1 2 3 4 5 6 7 8
16 VCC 15 1Rext/Cext 14 1Cext 13 1Q
12 2Q
11 2CLR
10 2B
9 2A
The SN74LV123A is a dual retriggerable monostable multivibrator designed for 2-V to 5.5-V VCC operation.
This edge-triggered multivibrator features output pulse-duration control by three methods. In the first method, the A input is low, and the B input goes high. In the second method, the B input is high, and the A input goes low. In the third method, the A input is low, the B input is high, and the clear (CLR) input goes high.
The output pulse duration is programmable by selecting external resistance and capacitance values. The external timing capacitor must be connected between Cext and Rext/Cext (positive) and an external resistor connected between Rext/Cext and VCC. To obtain variable pulse durations, connect an external variable resistance between Rext/Cext and VCC. The output pulse duration also can be reduced by taking CLR low.
Pulse triggering occurs at a particular voltage level and is not directly related to the transition time of the input pulse. The A, B, and CLR inputs have Schmitt triggers with sufficient hysteresis to handle slow input transition rates with jitter-free triggering at the outputs.
ORDERING INFORMATION
TA
PACKAGE‡
ORDERABLE PART NUMBER
TOP-SIDE MARKING
−40°C to 105°C TSSOP − PW Tape and reel SN74LV123ATPWREP L123AEP
‡ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
•POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright 2004, Texas Instruments Incorporated 1
SN74LV123AĆEP DUAL RETRIGGERABLE MONOSTABLE MULTIVIBRATOR WITH SCHMITTĆTRIGGER INPUTS
SCLS498A − MAY 2003 − REVISED MAY 2004
description/ordering information (continued)
Once triggered, the basic pulse duration can be extended by retriggering the gated low-level-active (A) or high-level-active (B) input. Pulse duration can be reduced by taking CLR low. The input/output timing diagram illustrates pulse control by retriggering the inputs and early clearing.
During power up, Q outputs are in the low state, and Q outputs are in the high state. The outputs are glitch free, without applying a reset pulse.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
FUNCTION TABLE (each multivibrator)
INPUTS
OUTPUTS
CLR A B Q Q
LXXLH X H X L† H† X X L L† H†
HL↑
H↓H
↑LH † These outputs are based on the
assumption that the indicated steady-state conditions at the A and B inputs have been set up long enough to complete any pulse started before the setup.
logic diagram, each multivibrator (positive logic)
A
Rext/Cext Cext
BQ
CLR
RQ
•2 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
input/output timin.