SN74LV125AT Buffer Gates Datasheet

SN74LV125AT Datasheet, PDF, Equivalent


Part Number

SN74LV125AT

Description

Quadruple Bus Buffer Gates

Manufacture

etcTI

Total Page 19 Pages
Datasheet
Download SN74LV125AT Datasheet


SN74LV125AT
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FEATURES
Inputs Are TTL-Voltage Compatible
4.5-V to 5.5-V VCC Operation
Typical tpd of 3.8 ns at 5 V
Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 5 V, TA = 25°C
Typical VOHV (Output VOH Undershoot)
>2.3 V at VCC = 5 V, TA = 25°C
Support Mixed-Mode Voltage Operation on All
Ports
D, DB, NS, OR PW PACKAGE
(TOP VIEW)
1OE
1A
1Y
2OE
2A
2Y
GND
1
2
3
4
5
6
7
14 VCC
13 4OE
12 4A
11 4Y
10 3OE
9 3A
8 3Y
SN74LV125AT
QUADRUPLE BUS BUFFER GATE
WITH 3-STATE OUTPUTS
SCES629A – MAY 2005 – REVISED AUGUST 2005
Ioff Supports Partial-Power-Down Mode
Operation
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
XXXX
XXXX
RGY PACKAGE
(TOP VIEW)
1A
1Y
2OE
2A
2Y
2
3
4
5
6
1
7
14
13 4OE
12 4A
11 4Y
10 3OE
9 3A
8
DESCRIPTION/ORDERING INFORMATION
The SN74LV125AT is a quadruple bus buffer gate. This device features independent line drivers with 3-state
outputs. Each output is disabled when the associated output-enable (OE) input is high.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
TA
–40°C to 85°C
QFN – RGY
SOIC – D
SOP – NS
SSOP – DB
TSSOP – PW
ORDERING INFORMATION
PACKAGE (1)
ORDERABLE PART NUMBER
Reel of 1000
SN74LV125ATRGYR
Tube of 50
SN74LV125ATD
Reel of 2500
SN74LV125ATDR
Tube of 50
SN74LV125ATNS
Reel of 2000
SN74LV125ATNSR
Tube of 80
SN74LV125ATDB
Reel of 2000
SN74LV125ATDBR
Tube of 90
SN74LV125ATPW
Reel of 2000
SN74LV125ATPWR
Reel of 250
SN74LV125ATPWT
TOP-SIDE MARKING
VV125
LV125AT
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005, Texas Instruments Incorporated

SN74LV125AT
SN74LV125AT
QUADRUPLE BUS BUFFER GATE
WITH 3-STATE OUTPUTS
SCES629A – MAY 2005 – REVISED AUGUST 2005
FUNCTION TABLE
(EACH BUFFER)
INPUTS
OE A
LH
LL
HX
OUTPUT
Y
H
L
Z
1
1OE
2
1A
4
2OE
5
2A
LOGIC DIAGRAM (POSITIVE LOGIC)
10
3OE
3
1Y
9
3A
13
4OE
6
2Y
12
4A
www.ti.com
8
3Y
11
4Y
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
VCC Supply voltage range
VI Input voltage range(2)
VO Voltage range applied to any output in the high-impedance or power-off state(2)
VO Output voltage range(2)(3)
IIK Input clamp current
VI < 0
IOK Output clamp current
VO < 0 or VO > VCC
IO Continuous output current
VO = 0 to VCC
Continuous current through VCC or GND
D package(4)
DB package(4)
θJA Package thermal impedance
NS package(4)
PW package(4)
RGY package(5)
Tstg Storage temperature range
MIN MAX UNIT
–0.5 7 V
–0.5 7 V
–0.5 7 V
–0.5
VCC + 0.5
–20
V
mA
±50 mA
±35 mA
±70 mA
86
96
76 °C/W
113
47
–65 150 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) This value is limited to 5.5 V maximum.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
(5) The package thermal impedance is calculated in accordance with JESD 51-5.
2


Features www.ti.com FEATURES • Inputs Are TTL-V oltage Compatible • 4.5-V to 5.5-V VC C Operation • Typical tpd of 3.8 ns a t 5 V • Typical VOLP (Output Ground B ounce) <0.8 V at VCC = 5 V, TA = 25°C • Typical VOHV (Output VOH Undershoot ) >2.3 V at VCC = 5 V, TA = 25°C • S upport Mixed-Mode Voltage Operation on All Ports D, DB, NS, OR PW PACKAGE (TO P VIEW) 1OE 1A 1Y 2OE 2A 2Y GND 1 2 3 4 5 6 7 14 VCC 13 4OE 12 4A 11 4Y 10 3OE 9 3A 8 3Y SN74LV125AT QUADRUPLE BU S BUFFER GATE WITH 3-STATE OUTPUTS SCES 629A – MAY 2005 – REVISED AUGUST 20 05 • Ioff Supports Partial-Power-Down Mode Operation • Latch-Up Performanc e Exceeds 250 mA Per JESD 17 • ESD Pr otection Exceeds JESD 22 – 2000-V Hum an-Body Model (A114-A) – 200-V Machin e Model (A115-A) – 1000-V Charged-Dev ice Model (C101) XXXX XXXX RGY PACKAGE (TOP VIEW) 1OE VCC 1A 1Y 2OE 2A 2Y 2 3 4 5 6 1 7 14 13 4OE 12 4A 11 4Y 10 3OE 9 3A 8 GND 3Y DESCRIPTION/ORDERI NG INFORMATION The SN74LV125AT is a quadruple bus buffer gate. This device features independe.
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