CD74HC4046A Phase-Locked Loop Datasheet

CD74HC4046A Datasheet, PDF, Equivalent


Part Number

CD74HC4046A

Description

Phase-Locked Loop

Manufacture

etcTI

Total Page 30 Pages
Datasheet
Download CD74HC4046A Datasheet


CD74HC4046A
Data sheet acquired from Harris Semiconductor
SCHS204J
February 1998 - Revised December 2003
CD54HC4046A, CD74HC4046A,
CD54HCT4046A, CD74HCT4046A
High-Speed CMOS Logic
Phase-Locked Loop with VCO
[ /Title
(CD74
HC404
6A,
CD74
HCT40
46A)
/Sub-
ject
(High-
Speed
CMOS
Features
Description
• Operating Frequency Range
- Up to 18MHz (Typ) at VCC = 5V
- Minimum Center Frequency of 12MHz at VCC = 4.5V
• Choice of Three Phase Comparators
- EXCLUSIVE-OR
- Edge-Triggered JK Flip-Flop
- Edge-Triggered RS Flip-Flop
• Excellent VCO Frequency Linearity
• VCO-Inhibit Control for ON/OFF Keying and for Low
Standby Power Consumption
• Minimal Frequency Drift
• Operating Power Supply Voltage Range
- VCO Section . . . . . . . . . . . . . . . . . . . . . . . . . . 3V to 6V
- Digital Section . . . . . . . . . . . . . . . . . . . . . . . . 2V to 6V
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il 1µA at VOL, VOH
Applications
The ’HC4046A and ’HCT4046A are high-speed silicon-gate
CMOS devices that are pin compatible with the CD4046B of
the “4000B” series. They are specified in compliance with
JEDEC standard number 7.
The ’HC4046A and ’HCT4046A are phase-locked-loop
circuits that contain a linear voltage-controlled oscillator
(VCO) and three different phase comparators (PC1, PC2 and
PC3). A signal input and a comparator input are common to
each comparator.
The signal input can be directly coupled to large voltage
signals, or indirectly coupled (with a series capacitor) to small
voltage signals. A self-bias input circuit keeps small voltage
signals within the linear region of the input amplifiers. With a
passive low-pass filter, the 4046A forms a second-order loop
PLL. The excellent VCO linearity is achieved by the use of
linear op-amp techniques.
Ordering Information
PART NUMBER
TEMP. RANGE
(oC)
PACKAGE
CD54HC4046AF3A
-55 to 125
16 Ld CERDIP
CD54HCT4046AF3A
-55 to 125
16 Ld CERDIP
CD74HC4046AE
-55 to 125
16 Ld PDIP
CD74HC4046AM
-55 to 125
16 Ld SOIC
CD74HC4046AMT
-55 to 125
16 Ld SOIC
CD74HC4046AM96
-55 to 125
16 Ld SOIC
CD74HC4046ANSR
-55 to 125
16 Ld SOP
CD74HC4046APWR
-55 to 125
16 Ld TSSOP
CD74HC4046APWT
-55 to 125
16 Ld TSSOP
CD74HCT4046AE
-55 to 125
16 Ld PDIP
CD74HCT4046AM
-55 to 125
16 Ld SOIC
CD74HCT4046AMT
-55 to 125
16 Ld SOIC
CD74HCT4046AM96
-55 to 125
16 Ld SOIC
NOTE: When ordering, use the entire part number. The suffixes 96
and R denote tape and reel. The suffix T denotes a small-quantity
reel of 250.
• FM Modulation and Demodulation
• Frequency Synthesis and Multiplication
• Frequency Discrimination
• Tone Decoding
• Data Synchronization and Conditioning
• Voltage-to-Frequency Conversion
• Motor-Speed Control
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
1

CD74HC4046A
CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A
Pinout
CD54HC4046A, CD54HCT4046A (CERDIP)
CD74HC4046A (PDIP, SOIC, SOP, TSSOP)
CD74HCT4046A (PDIP, SOIC)
TOP VIEW
PCPOUT 1
PC1OUT 2
COMPIN 3
VCOOUT 4
INH 5
C1A 6
C1B 7
GND 8
16 VCC
15 PC3OUT
14 SIGIN
13 PC2OUT
12 R2
11 R1
10 DEMOUT
9 VCOIN
Functional Diagram
3
COMPIN
14
SIGIN
C1A
C1B
R1
R2
VCOIN
INH
6
7
11
12
9
5
2
PC1OUT
15
φ
PC3OUT
13
PC2OUT
1
PCPOUT
VCO
4
VCOOUT
10
DEMOUT
Pin Descriptions
PIN NUMBER
SYMBOL
1 PCPOUT
2 PC1OUT
3 COMPIN
4 VCOOUT
5 INH
6 C1A
7 C1B
8 GND
9 VCOIN
10 DEMOUT
11 R1
12 R2
13 PC2OUT
14 SIGIN
15 PC3OUT
16 VCC
NAME AND FUNCTION
Phase Comparator Pulse Output
Phase Comparator 1 Output
Comparator Input
VCO Output
Inhibit Input
Capacitor C1 Connection A
Capacitor C1 Connection B
Ground (0V)
VCO Input
Demodulator Output
Resistor R1 Connection
Resistor R2 Connection
Phase Comparator 2 Output
Signal Input
Phase Comparator 3 Output
Positive Supply Voltage
2


Features Data sheet acquired from Harris Semicond uctor SCHS204J February 1998 - Revised December 2003 CD54HC4046A, CD74HC4046A , CD54HCT4046A, CD74HCT4046A High-Speed CMOS Logic Phase-Locked Loop with VCO [ /Title (CD74 HC404 6A, CD74 HCT40 46 A) /Subject (HighSpeed CMOS Features Description • Operating Frequency Ra nge - Up to 18MHz (Typ) at VCC = 5V - M inimum Center Frequency of 12MHz at VCC = 4.5V • Choice of Three Phase Compa rators - EXCLUSIVE-OR - Edge-Triggered JK Flip-Flop - Edge-Triggered RS Flip-F lop • Excellent VCO Frequency Lineari ty • VCO-Inhibit Control for ON/OFF K eying and for Low Standby Power Consump tion • Minimal Frequency Drift • Op erating Power Supply Voltage Range - VC O Section . . . . . . . . . . . . . . . . . . . . . . . . . . 3V to 6V - Digit al Section . . . . . . . . . . . . . . . . . . . . . . . . 2V to 6V • Fanout (Over Temperature Range) - Standard Ou tputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads • W.
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