CD74HC40105 FIFO Register Datasheet

CD74HC40105 Datasheet, PDF, Equivalent


Part Number

CD74HC40105

Description

4-Bit x 16-Word FIFO Register

Manufacture

etcTI

Total Page 22 Pages
Datasheet
Download CD74HC40105 Datasheet


CD74HC40105
Data sheet acquired from Harris Semiconductor
SCHS222C
February 1998 - Revised October 2003
CD54HC40105, CD74HC40105,
CD54HCT40105, CD74HCT40105
High-Speed CMOS Logic
4-Bit x 16-Word FIFO Register
[ /Title
(CD74
HC401
05,
CD74
HCT40
105)
/Sub-
ject
(High
Speed
CMOS
Features
Description
• Independent Asynchronous Inputs and Outputs
• Expandable in Either Direction
• Reset Capability
• Status Indicators on Inputs and Outputs
• Three-State Outputs
• Shift-Out Independent of Three-State Control
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il 1µA at VOL, VOH
Applications
• Bit-Rate Smoothing
• CPU/Terminal Buffering
• Data Communications
• Peripheral Buffering
• Line Printer Input Buffers
• Auto-Dialers
• CRT Buffer Memories
• Radar Data Acquisition
The ’HC40105 and ’HCT40105 are high-speed silicon-gate
CMOS devices that are compatible, except for “shift-out”
circuitry, with the CD40105B. They are low-power first-in-out
(FIFO) “elastic” storage registers that can store 16 four-bit
words. The 40105 is capable of handling input and output
data at different shifting rates. This feature makes it
particularly useful as a buffer between asynchronous
systems.
Each work position in the register is clocked by a control flip-
flop, which stores a marker bit. A “1” signifies that the posi-
tion’s data is filled and a “0” denotes a vacancy in that posi-
tion. The control flip-flop detects the state of the preceding
flip-flop and communicates its own status to the succeeding
flip-flop. When a control flip-flop is in the “0” state and sees a
“1” in the preceeding flip-flop, it generates a clock pulse that
transfers data from the preceding four data latches into its
own four data latches and resets the preceding flip-flop to
“0”. The first and last control flip-flops have buffered outputs.
Since all empty locations “bubble” automatically to the input
end, and all valid data ripple through to the output end, the
status of the first control flip-flop (DATA-IN READY) indicates
if the FIFO is full, and the status of the last flip-flop (DATA-
OUT READY) indicates if the FIFO contains data. As the
earliest data are removed from the bottom of the data stack
(the output end), all data entered later will automatically
propagate (ripple) toward the output.
Ordering Information
PART NUMBER
CD54HC40105F3A
CD54HCT40105F3A
CD74HC40105E
CD74HC40105M
CD74HC40105MT
CD74HC40105M96
CD74HCT40105E
CD74HCT40105M
CD74HCT40105MT
TEMP. RANGE (oC) PACKAGE
-55 to 125
16 Ld CERDIP
-55 to 125
16 Ld CERDIP
-55 to 125
16 Ld PDIP
-55 to 125
16 Ld SOIC
-55 to 125
16 Ld SOIC
-55 to 125
16 Ld SOIC
-55 to 125
16 Ld PDIP
-55 to 125
16 Ld SOIC
-55 to 125
16 Ld SOIC
CD74HCT40105M96
-55 to 125
16 Ld SOIC
NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel. The suffix T denotes a small-quantity reel
of 250.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
1

CD74HC40105
CD54HC40105, CD74HC40105, CD54HCT40105, CD74HCT40105
Pinout
CD54HC40105, CD54HCT40105
(CERDIP)
CD74HC40105, CD74HCT40105
(PDIP, SOIC)
TOP VIEW
THREE-STATE
CONTROL
1
DIR 2
SI 3
D0 4
D1 5
D2 6
D3 7
GND 8
16 VCC
15 SO
14 DOR
13 Q0
12 Q1
11 Q2
10 Q3
9 MR
Loading Data
Data can be entered whenever the DATA-IN READY (DIR)
flag is high, by a low to high transition on the SHIFT-IN (SI)
input. This input must go low momentarily before the next
word is accepted by the FIFO. The DIR flag will go low
momentarily, until the data have been transferred to the sec-
ond location. The flag will remain low when all 16-word loca-
tions are filled with valid data, and further pulses on the SI
input will be ignored until DIR goes high.
Unloading Data
As soon as the first word has rippled to the output, the data-
out ready output (DOR) goes HIGH and data of the first word
is available on the outputs. Data of other words can be
removed by a negative-going transition on the shift-out input
(SO). This negative-going transition causes the DOR signal
to go LOW while the next word moves to the output. As long
as valid data is available in the FIFO, the DOR signal will go
high again, signifying that the next word is ready at the
output. When the FIFO is empty, DOR will remain LOW, and
any further commands will be ignored until a “1” marker
ripples down to the last control register and DOR goes
HIGH. If during unloading SI is HIGH, (FIFO is full) data on
the data input of the FIFO is entered in the first location.
Three-State Outputs
In order to facilitate data busing, three-state outputs (Q0 to
Q3) are provided on the data output lines, while the load
condition of the register can be detected by the state of the
DOR output. A HIGH on the three-state control flag (output
enable input OE) forces the outputs into the high-impedance
OFF-state mode. Note that the shift-out signal, unlike that in
the CD40105B, is independent of the three-state output
control. In the CD40105B, the three-state control must not
be shifted from High to Low when the shift-out signal is Low
(data loss would occur). In the high-speed CMOS version
this restriction has been eliminated.
Cascading
The 40105 can be cascaded to form longer registers simply
by connecting the DIR to SO and DOR to SI. In the cascaded
mode, a MASTER RESET pulse must be applied after the
supply voltage is turned on. For words wider than four bits, the
DIR and the DOR outputs must be gated together with AND
gates. Their outputs drive the SI and SO inputs in parallel, if
expanding is done in both directions (see Figures 12 and 13).
Functional Diagram
THREE-
STATE
CONTROL
4
D0
5
D1
6
D2
7
D3
1
13 Q0
12
Q1
11
Q2
10
Q3
3
SHIFT IN
15
SHIFT OUT
MASTER
RESET
14 DATA-OUT
READY
2 DATA-IN
READY
9 GND = 8
VCC = 16
Master Reset
A high on the MASTER RESET (MR) sets all the control
logic marker bits to “0”. DOR goes low and DIR goes high.
The contents of the data register are not changed, only
declared invalid, and will be superseded when the first word
is loaded. Thus, MR does not clear data within the register
but only the control logic. If the shift-in flag (SI) is HIGH
during the master reset pulse, data present at the input (D0
to D3) are immediately moved into the first location upon
completion of the reset process.
2


Features Data sheet acquired from Harris Semicond uctor SCHS222C February 1998 - Revised October 2003 CD54HC40105, CD74HC40105, CD54HCT40105, CD74HCT40105 High-Speed CMOS Logic 4-Bit x 16-Word FIFO Registe r [ /Title (CD74 HC401 05, CD74 HCT40 105) /Subject (High Speed CMOS Feature s Description • Independent Asynchr onous Inputs and Outputs • Expandable in Either Direction • Reset Capabili ty • Status Indicators on Inputs and Outputs • Three-State Outputs • Shi ft-Out Independent of Three-State Contr ol • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver O utputs . . . . . . . . . . . . . 15 LST TL Loads • Wide Operating Temperature Range . . . -55oC to 125oC • Balance d Propagation Delay and Transition Time s • Significant Power Reduction Comp ared to LSTTL Logic ICs • HC Types - 2V to 6V Operation - High Noise Immunit y: NIL = 30%, NIH = 30% of VCC at VCC = 5V • HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL=.
Keywords CD74HC40105, datasheet, pdf, etcTI, 4-Bit, x, 16-Word, FIFO, Register, D74HC40105, 74HC40105, 4HC40105, CD74HC4010, CD74HC401, CD74HC40, Equivalent, stock, pinout, distributor, price, schematic, inventory, databook, Electronic, Components, Parameters, parts, cross reference, chip, Semiconductor, circuit, Electric, manual, substitute




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