CD74HCT4020 Binary Counter Datasheet

CD74HCT4020 Datasheet, PDF, Equivalent


Part Number

CD74HCT4020

Description

14-Stage Binary Counter

Manufacture

etcTI

Total Page 16 Pages
Datasheet
Download CD74HCT4020 Datasheet


CD74HCT4020
Data sheet acquired from Harris Semiconductor
SCHS201C
February 1998 - Revised October 2003
CD54HC4020, CD74HC4020,
CD54HCT4020, CD74HCT4020
High-Speed CMOS Logic
14-Stage Binary Counter
[ /Title
(CD74
HC402
0,
CD74
HCT40
20)
/Sub-
ject
(High
Speed
CMOS
Features
Description
• Fully Static Operation
• Buffered Inputs
• Common Reset
• Negative Edge Clocking
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il 1µA at VOL, VOH
The ’HC4020 and ’HCT4020 are 14-stage ripple-carry
binary counters. All counter stages are master-slave flip-
flops. The state of the stage advances one count on the
negative clock transition of each input pulse; a high voltage
level on the MR line resets all counters to their zero state. All
inputs and outputs are buffered.
Ordering Information
PART NUMBER
CD54HC4020F3A
CD54HCT4020F3A
CD74HC4020E
CD74HC4020M
CD74HC4020MT
CD74HC4020M96
CD74HCT4020E
CD74HCT4020M
CD74HCT4020MT
CD74HCT4020M96
TEMP. RANGE
(oC)
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
PACKAGE
16 Ld CERDIP
16 Ld CERDIP
16 Ld PDIP
16 Ld SOIC
16 Ld SOIC
16 Ld SOIC
16 Ld PDIP
16 Ld SOIC
16 Ld SOIC
16 Ld SOIC
NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel. The suffix T denotes a small-quantity reel
of 250.
Pinout
CD54HC4020, CD54HCT4020
(CERDIP)
CD74HC4020, CD74HCT4020
(PDIP, SOIC)
TOP VIEW
Q12 1
Q13 2
Q14 3
Q6 4
Q5 5
Q7 6
Q4 7
GND 8
16 VCC
15 Q11
14 Q10
13 Q8
12 Q9
11 MR
10 CP
9 Q1
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
1

CD74HCT4020
CD54HC4020, CD74HC4020, CD54HCT4020, CD74HCT4020
Functional Diagram
VCC
16
10
INPUT
PULSES
11
MASTER
RESET
14-STAGE
RIPPLE
COUNTER
8
GND
9
Q1’
7
Q4
5
Q5
4
Q6
6
Q7
13
Q8
12
Q9
14
Q10
15
Q11
1
Q12
2
Q13
3
Q14
BUFFERED
OUTPUTS
TRUTH TABLE
CP COUNT
MR
OUTPUT STATE
L
No Change
L
Advance to Next State
XH
All Outputs Are Low
H = High Voltage Level, L = Low Voltage Level, X = Don’t Care,
= Transition from Low to High Level, = Transition from High to Low.
2


Features Data sheet acquired from Harris Semicond uctor SCHS201C February 1998 - Revised October 2003 CD54HC4020, CD74HC4020, C D54HCT4020, CD74HCT4020 High-Speed CMOS Logic 14-Stage Binary Counter [ /Titl e (CD74 HC402 0, CD74 HCT40 20) /Subjec t (High Speed CMOS Features Descripti on • Fully Static Operation • Buff ered Inputs • Common Reset • Negati ve Edge Clocking • Fanout (Over Tempe rature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads • Wide Operati ng Temperature Range . . . -55oC to 125 oC • Balanced Propagation Delay and T ransition Times • Significant Power Reduction Compared to LSTTL Logic ICs HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% o f VCC at VCC = 5V • HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), V IH = 2V (Min) - CMOS Input Compatibilit y, Il ≤ 1µA at VOL, VOH The ’HC4020 and ’HCT4020 are 14-stage ripple-carry binary co.
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