CD74HCT4024

Data sheet acquired from Harris Semiconductor SCHS202C November 1997 - Revised October 2003 CD54HC4024, CD74HC4024, CD54HCT4024, CD74HCT4024 High-Speed CMOS Logic 7-Stage Binary Ripple Counter [ /Title (CD74 HC402 4, CD74 HCT40 24) /Subject (High Speed CMOS Features Description Fully Static Operation Buffered Inputs Common Reset Negative Edge Clocking Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads Wide Operating Temperature Range . . . -55oC to 125oC Balanced Propagation Delay and Transition Times Significant Power Reduction Compared to LSTTL Logic ICs HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH The ’HC4024 and ’HCT4024 are 7-stage ripple-carry binary counters. All counter stages are master-slave flip-flops. The state of the stage advances one count on the negative transition of each input pulse; a high voltage level on the MR line resets all counters to their zero state. All inputs and outputs are buffered. Ordering Information PART NUMBER CD54HC4024F3A CD54HCT4024F3A CD74HC4024E CD74HC4024M CD74HC4024MT CD74HC4024M96 CD74HC4024PW CD74HC4024PWR CD74HC4024PWT CD74HCT4024E TEMP. RANGE (oC) -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to...