CD54HC4060 Binary Counter Datasheet

CD54HC4060 Datasheet, PDF, Equivalent


Part Number

CD54HC4060

Description

14-Stage Binary Counter

Manufacture

etcTI

Total Page 21 Pages
Datasheet
Download CD54HC4060 Datasheet


CD54HC4060
Data sheet acquired from Harris Semiconductor
SCHS207G
February 1998 - Revised October 2003
CD54HC4060, CD74HC4060,
CD54HCT4060, CD74HCT4060
High-Speed CMOS Logic
14-Stage Binary Counter with Oscillator
[ /Title
(CD74
HC406
0,
CD74
HCT40
60)
/Sub-
ject
(High
Speed
CMOS
Features
• Onboard Oscillator
• Common Reset
• Negative-Edge Clocking
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il 1µA at VOL, VOH
Description
The ’HC4060 and ’HCT4060 each consist of an oscillator
section and 14 ripple-carry binary counter stages. The
oscillator configuration allows design of either RC or crystal
oscillator circuits. A Master Reset input is provided which
resets the counter to the all-0’s state and disables the
oscillator. A high level on the MR line accomplishes the reset
function. All counter stages are master-slave flip-flops. The
state of the counter is advanced one step in binary order on
the negative transition of φI (and φO). All inputs and outputs
are buffered. Schmitt trigger action on the input-pulse-line
permits unlimited rise and fall times.
In order to achieve a symmetrical waveform in the oscillator
section the HCT4060 input pulse switch points are the same
as in the HC4060; only the MR input in the HCT4060 has
TTL switching levels.
Ordering Information
PART NUMBER
TEMP. RANGE
(oC)
PACKAGE
CD54HC4060F3A
-55 to 125
16 Ld CERDIP
CD54HCT4060F3A
-55 to 125
16 Ld CERDIP
CD74HC4060E
-55 to 125
16 Ld PDIP
CD74HC4060M
-55 to 125
16 Ld SOIC
CD74HC4060MT
-55 to 125
16 Ld SOIC
CD74HC4060M96
-55 to 125
16 Ld SOIC
CD74HC4060PW
-55 to 125
16 Ld TSSOP
CD74HC4060PWR
-55 to 125
16 Ld TSSOP
CD74HC4060PWT
-55 to 125
16 Ld TSSOP
CD74HCT4060E
-55 to 125
16 Ld PDIP
CD74HCT4060M
-55 to 125
16 Ld SOIC
CD74HCT4060MT
-55 to 125
16 Ld SOIC
CD74HCT4060M96
-55 to 125
16 Ld SOIC
NOTE: When ordering, use the entire part number. The suffixes 96
and R denote tape and reel. The suffix T denotes a small-quantity
reel of 250.
Pinout
CD54HC4060, CD54HCT4060 (CERDIP)
CD74HC4060 (PDIP, SOIC, TSSOP)
CD74HCT4060 (PDIP, SOIC)
TOP VIEW
Q12 1
Q13 2
Q14 3
Q6 4
Q5 5
Q7 6
Q4 7
GND 8
16 VCC
15 Q10
14 Q8
13 Q9
12 MR
11 φI
10 φO
9 φO
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
1

CD54HC4060
Functional Diagram
CD54/74HC4060, CD54/74HCT4060
12
MR
11
φI
14-STAGE
RIPPLE
COUNTER
AND
OSCILLATOR
7
Q4
5
Q5
4
Q6
6
Q7
14
Q8
13
Q9
15
Q10
1
Q12
2
Q13
3
Q14
9
φO
10
φO
GND = 8
VCC = 16
øO 9
10
øO
11
ø1
12
MR
ø1 Q1
FF1
ø1 Q1
R
ø4 Q4
FF4
ø4 Q4
R
ø5 Q13
FF5 - FF13
ø5 Q13
R
ø14 Q14
FF14
ø14 Q14
R
72
Q4 5, 4, 6, 14, 13, 15, 1 Q13
Q5 - Q10, Q12
FIGURE 1. LOGIC BLOCK DIAGRAM
TRUTH TABLE
øI MR OUTPUT STATE
L No Change
L Advance to Next State
X H All Outputs are Low
3
Q14
2


Features Data sheet acquired from Harris Semicond uctor SCHS207G February 1998 - Revised October 2003 CD54HC4060, CD74HC4060, C D54HCT4060, CD74HCT4060 High-Speed CMOS Logic 14-Stage Binary Counter with Osc illator [ /Title (CD74 HC406 0, CD74 H CT40 60) /Subject (High Speed CMOS Fea tures • Onboard Oscillator • Common Reset • Negative-Edge Clocking • F anout (Over Temperature Range) - Standa rd Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads • Wide Operating Temperature Range . . . -55oC to 125oC • Balanced Propag ation Delay and Transition Times • Si gnificant Power Reduction Compared to LSTTL Logic ICs • HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V • HCT Types - 4.5V to 5.5V Operation - Di rect LSTTL Input Logic Compatibility, V IL= 0.8V (Max), VIH = 2V (Min) - CMOS I nput Compatibility, Il ≤ 1µA at VOL, VOH Description The ’HC4060 and ’HCT4060 each consist of an oscillator section and 14.
Keywords CD54HC4060, datasheet, pdf, etcTI, 14-Stage, Binary, Counter, D54HC4060, 54HC4060, 4HC4060, CD54HC406, CD54HC40, CD54HC4, Equivalent, stock, pinout, distributor, price, schematic, inventory, databook, Electronic, Components, Parameters, parts, cross reference, chip, Semiconductor, circuit, Electric, manual, substitute




@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact)