CD54HCT4075 OR Gate Datasheet

CD54HCT4075 Datasheet, PDF, Equivalent


Part Number

CD54HCT4075

Description

Triple 3-Input OR Gate

Manufacture

etcTI

Total Page 22 Pages
Datasheet
Download CD54HCT4075 Datasheet


CD54HCT4075
Data sheet acquired from Harris Semiconductor
SCHS210G
August 1997 - Revised June 2006
CD54HC4075, CD74HC4075,
CD54HCT4075, CD74HCT4075
High-Speed CMOS Logic
Triple 3-Input OR Gate
[ /Title
(CD74H
C4075,
CD74H
CT4075)
/Subject
(High
Speed
CMOS
Logic
Triple 3-
Input
Features
Description
• Buffered Inputs
Typical Propagation Delay:
CL = 15pF, TA = 25oC
8ns
at
VCC
=
5V,
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il 1µA at VOL, VOH
The ’HC4075 and ’HCT4075 logic gates utilize silicon-gate
CMOS technology to achieve operating speeds similar to
LSTTL gates with the low power consumption of standard
CMOS integrated circuits. All devices have the ability to drive
10 LSTTL loads. The HCT logic family is functionally pin
compatible with the standard LS logic family.
Ordering Information
PART NUMBER
CD54HC4075F3A
CD54HC4075FK
CD54HCT4075F3A
CD74HC4075E
CD74HC4075M
CD74HC4075MT
CD74HC4075M96
CD74HC4075NSR
CD74HC4075PW
TEMP. RANGE
(oC)
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
PACKAGE
14 Ld CERDIP
20 LCCC
14 Ld CERDIP
14 Ld PDIP
14 Ld SOIC
14 Ld SOIC
14 Ld SOIC
14 Ld SOP
14 Ld TSSOP
CD74HC4075PWR
-55 to 125
14 Ld TSSOP
CD74HC4075PWT
-55 to 125
14 Ld TSSOP
CD74HCT4075E
-55 to 125
14 Ld PDIP
NOTE: When ordering, use the entire part number. The suffixes 96
and R denote tape and reel. The suffix T denotes a small-quantity
reel of 250.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2006, Texas Instruments Incorporated
1

CD54HCT4075
Pinout
CD54HC4075, CD74HC4075, CD54HCT4075, CD74HCT4075
CD54HC4075, CD54HCT4075 (CERDIP)
CD74HC4075 (PDIP, SOIC, SOP, TSSOP)
CD74HCT4075 (PDIP)
TOP VIEW
2A 1
2B 2
1A 3
1B 4
1C 5
1Y 6
GND 7
14 VCC
13 3C
12 3B
11 3A
10 3Y
9 2Y
8 2C
SN54HC4075 (FK)
(TOP VIEW)
3 2 1 20 19
1A 4
18 3B
NC 5
17 NC
1B 6
16 3A
NC 7
15 NC
1C 8
14 3Y
9 10 11 12 13
2


Features Data sheet acquired from Harris Semicond uctor SCHS210G August 1997 - Revised Ju ne 2006 CD54HC4075, CD74HC4075, CD54HC T4075, CD74HCT4075 High-Speed CMOS Logi c Triple 3-Input OR Gate [ /Title (CD7 4H C4075, CD74H CT4075) /Subject (High Speed CMOS Logic Triple 3Input Feature s Description • Buffered Inputs Typical Propagation Delay: CL = 15pF , TA = 25oC 8ns at VCC = 5V, • Fanout (Over Temperature Range) - Stan dard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Output s . . . . . . . . . . . . . 15 LSTTL Lo ads • Wide Operating Temperature Ran ge . . . -55oC to 125oC • Balanced P ropagation Delay and Transition Times • Significant Power Reduction Compar ed to LSTTL Logic ICs • HC Types - 2 V to 6V Operation - High Noise Immunity : NIL = 30%, NIH = 30% of VCC at VCC = 5V • HCT Types - 4.5V to 5.5V Operati on - Direct LSTTL Input Logic Compatibi lity, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH The ’HC4075 and ’HCT4075 logic g.
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