CD74HCT4075

CD74HCT4075, CD54HCT4075 SCHS408 – JUNE 2020 CDx4HCT4075 Triple 3-Input OR Gates 1 Features LSTTL input logic compatible – VIL(max) = 0.8 V, VIH(min) = 2 V CMOS input logic compatible – II ≤ 1 µA at VOL, VOH Buffered inputs 4.5 V to 5.5 V operation Wide operating temperature range: -55°C to +125°C Supports fanout up to 10 LSTTL loads Significant power reduction compared to LSTTL logic ICs 2 Applications User fewer inputs to monitor error signals Combine active-low enable signals 3 Description This device contains three independent 3-input OR gates. Each gate performs the Boolean function Y = A + B + C in positive logic. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) CD74HCT4075E PDIP (14) 19.30 mm × 6.40 mm CD54HCT4075F CDIP (14) 21.30 mm × 7.60 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. 2A 1 2B 2 1A 3 1B 4 1C 5 1Y 6 GND 7 14 VCC 13 3C 12 3B 11 3A 10 3Y 9 2Y 8 2C Functional pinout An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. CD74HCT4075, CD54HCT4075 SCHS408 – JUNE 2020 www.ti.com Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description............