CD54HC4094 Bus Register Datasheet

CD54HC4094 Datasheet, PDF, Equivalent


Part Number

CD54HC4094

Description

8-Stage Shift and Store Bus Register

Manufacture

etcTI

Total Page 22 Pages
Datasheet
Download CD54HC4094 Datasheet


CD54HC4094
CD54HC4094, CD74HC4094,
CD74HCT4094
Data sheet acquired from Harris Semiconductor
SCHS211E
November 1997 Revised December 2010
HighSpeed CMOS Logic
8Stage Shift and Store Bus Register, ThreeState
[ /Title
(CD74H
C4094,
CD74H
CT4094
)
/Sub
ject
(High
Speed
CMOS
Logic 8
Features
¥ Buffered Inputs
¥ Separate Serial Outputs Synchronous to Both
Positive and Negative Clock Edges For Cascading
¥ Fanout (Over Temperature Range)
Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
¥ Wide Operating T emperature Rang e . . . 55oC to 125oC
¥ Balanced Propagation Delay and Transition Times
¥ Signi cant Power Reduction Compared to LSTTL
Logic ICs
¥ HC Types
2V to 6V Operation
High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V
¥ HCT Types
4.5V to 5.5V Operation
Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
CMOS Input Compatibility, Il 1μA at VOL, VOH
Description
The ÕHC4094and CD74HCT4094 are 8stage serial shift
registers having a storage latch associated with each stage
for strobing data from the serial input to parallel buffered
threestate outputs. The parallel outputs may be connected
directly to common bus lines. Data is shifted on positive
clock transitions. The data in each shift register stage is
transferred to the storage register when the Strobe input is
high. Data in the storage register appears at the outputs
whenever the OutputEnable signal is high.
Two serial outputs are available for cascading a number of
these devices. Data is available at the QS1 serial output
terminal on positive clock edges to allow for highspeed
operation in cascaded system in which the clock rise time is
fast. The same serial information, available at the QS2
terminal on the next negative clock edge, provides a means
for cascading these devices when the clock rise time is slow.
Ordering Information
PART NUMBER
TEMP. RANGE
(oC)
PACKAGE
CD54HC4094F3A
55 to 125
16 Ld CERDIP
CD74HC4094E
55 to 125
16 Ld PDIP
CD74HC4094M
55 to 125
16 Ld SOIC
CD74HC4094MT
55 to 125
16 Ld SOIC
CD74HC4094M96G3
55 to 125
16 Ld SOIC
CD74HC4094NSR
55 to 125
16 Ld SOP
CD74HC4094PW
55 to 125
16 Ld TSSOP
CD74HC4094PWR
55 to 125
16 Ld TSSOP
CD74HC4094PWT
55 to 125
16 Ld TSSOP
CD74HCT4094E
55 to 125
16 Ld PDIP
CD74HCT4094M
55 to 125
16 Ld SOIC
CD74HCT4094MT
55 to 125
16 Ld SOIC
CD74HCT4094M96
55 to 125
16 Ld SOIC
NOTE: When ordering, use the entire part number. The suf xes 96
and R denote tape and reel. The suf x T denotes a smallquantity
reel of 250.
Pinout
CD54HC4094 (CERDIP)
CD74HC4094 (PDIP, SOIC, SOP, TSSOP)
CD74HCT4094 (PDIP, SOIC)
TOP VIEW
STROBE 1
DATA 2
CP 3
Q0
Q1
Q2
Q3
GND
4
5
6
7
8
16 VCC
15 OE
14 Q4
13 Q5
12 Q6
11 Q7
10 QS2
9 QS1
CAUTION: These devices are sensitive to electrostatic discharge . Users should follow proper IC Handling Procedures .
Copyright 2003, Texas Instruments Incorporated
1

CD54HC4094
CD54HC4094, CD74HC4094, CD74HCT4094
Functional Diagram
DATA
CP
2
3
8STAGE
SHIFT
REGISTER
9
QS1
10
QS2
1
STROBE
8BIT
STORAGE
REGISTER
15
OE
THREE
STATE
OUTPUT
4
5 Q0
6 Q1
7 Q2
14 Q3
13 Q4
12
11
Q5
Q6
Q7
GND = 8
VCC = 16
TRUTH TABLE
INPUTS
PARALLEL OUTPUTS
SERIAL OUTPUTS
CP
OE STR D
Q0
Qn
QS1 (NOTE 1)
QS2
L
X
X
Z
Z
QÕ6
NC
L X X Z Z NC Q7
H
L
X
NC
NC
QÕ6
NC
H
HL
L
Qn 1
QÕ6
NC
H
H
H
H
Qn 1
QÕ6
NC
H H H NC NC NC Q7
H = High Voltage Level, L = Low Voltage Level, X = DonÕt Care, NC = No charge, Z = High Impedance Offstate,
↑ = Transition from Low to High Level, = Transition from High to Low.
NOTE:
1. At the positive clock edge the information in the seventh register stage is transferred to the 8th register stage and QS1 output.
2


Features CD54HC4094, CD74HC4094, CD74HCT4094 Dat a sheet acquired from Harris Semiconduc tor SCHS211E November 1997 − Revised December 2010 High−Speed CMOS Logic 8−Stage Shift and Store Bus Register, Three−State [ /Title (CD74H C4094, CD74H CT4094 ) /Sub− ject (High Speed CMOS Logic 8− Features ¥ Buffered Inputs ¥ Separate Serial Outputs Synch ronous to Both Positive and Negative Cl ock Edges For Cascading ¥ Fanout (Over Temperature Range) − Standard Output s . . . . . . . . . . . . . . . 10 LSTT L Loads − Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads ¥ Wid e Operating T emperature Rang e . . . 55oC to 125oC ¥ Balanced Propagation Delay and Transition Times ¥ Signi ca nt Power Reduction Compared to LSTTL Lo gic ICs ¥ HC Types − 2V to 6V Operat ion − High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V ¥ HCT Ty pes − 4.5V to 5.5V Operation − Dire ct LSTTL Input Logic Compatibility, VIL = 0.8V (Max), VIH = 2V (Min) − CMOS Input Compatibility, Il ≤ 1μA at VOL, VOH Description The ÕHC.
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