CD74HCT4094

CD54HC4094, CD74HC4094, CD74HCT4094 Data sheet acquired from Harris Semiconductor SCHS211E November 1997 − Revised December 2010 High−Speed CMOS Logic 8−Stage Shift and Store Bus Register, Three−State [ /Title (CD74H C4094, CD74H CT4094 ) /Sub− ject (High Speed CMOS Logic 8− Features ¥ Buffered Inputs ¥ Separate Serial Outputs Synchronous to Both Positive and Negative Clock Edges For Cascading ¥ Fanout (Over Temperature Range) − Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads − Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads ¥ Wide Operating T emperature Rang e . . . −55oC to 125oC ¥ Balanced Propagation Delay and Transition Times ¥ Signi cant Power Reduction Compared to LSTTL Logic ICs ¥ HC Types − 2V to 6V Operation − High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V ¥ HCT Types − 4.5V to 5.5V Operation − Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) − CMOS Input Compatibility, Il ≤ 1μA at VOL, VOH Description The ÕHC4094and CD74HCT4094 are 8−stage serial shift registers having a storage latch associated with each stage for strobing data from the serial input to parallel buffered three−state outputs. The parallel outputs may be connected directly to common bus lines. Data is shifted on positive clock transitions. The data in each shift register stage is transferred to the storage register when the Strobe input is high. Data in the storage register appears at the outputs whenever the Output−Enable signal is h...