CD74HC40103-EP DOWN COUNTER Datasheet

CD74HC40103-EP Datasheet, PDF, Equivalent


Part Number

CD74HC40103-EP

Description

8-STAGE SYNCHRONOUS DOWN COUNTER

Manufacture

etcTI

Total Page 15 Pages
Datasheet
Download CD74HC40103-EP Datasheet


CD74HC40103-EP
D Controlled Baseline
− One Assembly/Test Site, One Fabrication
Site
D Extended Temperature Performance of
−40°C to 125°C
D Enhanced Diminishing Manufacturing
Sources (DMS) Support
D Enhanced Product-Change Notification
D Qualification Pedigree
D Synchronous or Asynchronous Preset
D Cascadable in Synchronous or Ripple
Mode
D Fanout (Over Temperature Range)
− Standard Outputs . . . 10 LSTTL Loads
− Bus Driver Outputs . . . 15 LSTTL Loads
Component qualification in accordance with JEDEC and industry
standards to ensure reliable operation over an extended
temperature range. This includes, but is not limited to, Highly
Accelerated Stress Test (HAST) or biased 85/85, temperature
cycle, autoclave or unbiased HAST, electromigration, bond
intermetallic life, and mold compound life. Such qualification
testing should not be viewed as justifying use of this component
beyond specified performance and environmental limits.
CD74HC40103ĆEP
HIGHĆSPEED CMOS LOGIC
8ĆSTAGE SYNCHRONOUS DOWN COUNTER
SCLS548 − DECEMBER 2003
D Balanced Propagation Delay and Transition
Times
D Significant Power Reduction Compared to
LSTTL Logic ICs
D VCC Voltage = 2 V to 6 V
D High Noise Immunity NIL or NIH = 30% of
VCC, VCC = 5 V
M PACKAGE
(TOP VIEW)
CP
MR
TE
P0
P1
P2
P3
GND
1
2
3
4
5
6
7
8
16 VCC
15 PE (SYNC)
14 TC
13 P7
12 P6
11 P5
10 P4
9 PL (ASYNC)
description/ordering information
The CD74HC40103 is manufactured with high-speed silicon-gate technology and consists of an 8-stage
synchronous down counter with a single output, which is active when the internal count is zero. The device
contains a single 8-bit binary counter. Each device has control inputs for enabling or disabling the clock, for
clearing the counter to its maximum count, and for presetting the counter either synchronously or
asynchronously. All control inputs and the terminal count (TC) output are active-low logic.
In normal operation, the counter is decremented by one count on each positive transition of the clock (CP)
output. Counting is inhibited when the terminal enable (TE) input is high. TC goes low when the count reaches
zero, if TE is low, and remains low for one full clock period.
When the synchronous preset enable (PE) input is low, data at the P0−P7 inputs are clocked into the counter on
the next positive clock transition, regardless of the state of TE. When the asynchronous preset enable (PL) input
is low, data at the P0−P7 inputs asynchronously are forced into the counter, regardless of the state of the PE, TE,
or CP inputs. Inputs P0−P7 represent a single 8-bit binary word for the CD74HC40103. When the master reset
(MR) input is low, the counter asynchronously is cleared to its maximum count of 25510, regardless of the state of
any other input. The precedence relationship between control inputs is indicated in the truth table.
ORDERING INFORMATION
TA
PACKAGE‡
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
−40°C to 125°C SOIC − M
Tape and reel CD74HC40103QM96EP HC40103QEP
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright 2003, Texas Instruments Incorporated
1

CD74HC40103-EP
CD74HC40103ĆEP
HIGHĆSPEED CMOS LOGIC
8ĆSTAGE SYNCHRONOUS DOWN COUNTER
SCLS548 − DECEMBER 2003
description/ordering information (continued)
If all control inputs except TE are high at the time of zero count, the counters jump to the maximum count, giving a
counting sequence of 10016 or 25610 clock pulses long.
The CD74HC40103 may be cascaded using the TE input and the TC output in either synchronous or ripple
mode. These circuits have the low power consumption usually associated with CMOS circuitry, yet have speeds
comparable to low-power Schottky TTL circuits and can drive up to ten LSTTL loads.
FUNCTION TABLE†
CONTROL INPUTS
MR PL PE TE
PRESET MODE
ACTION
HHHH
Inhibit counter
HHH L
HHL X
Synchronous
Count down
Preset on next positive clock transition
HLXX
LXXX
Asynchronous
Preset asynchronously
Clear to maximum count
See Figure 2 for timing diagram.
NOTE: H = high voltage level, L = low voltage level, X = don’t care
Clock connected to clock input
Synchronous operation: changes occur on negative-to-positive clock transitions.
Load inputs: MSB = P7, LSB = P0
logic diagram (positive logic)
14
13 P7
12 P6
11 P5
10 P4
7 P3
6 P2
5 P1
P0
4
15 9 3 1 2
16 8
2 POST OFFICE BOX 655303 DALLAS, TEXAS 75265


Features D Controlled Baseline − One Assembly/T est Site, One Fabrication Site D Extend ed Temperature Performance of −40°C to 125°C D Enhanced Diminishing Manufa cturing Sources (DMS) Support D Enhance d Product-Change Notification D Qualifi cation Pedigree† D Synchronous or Asy nchronous Preset D Cascadable in Synchr onous or Ripple Mode D Fanout (Over Tem perature Range) − Standard Outputs . . . 10 LSTTL Loads − Bus Driver Outpu ts . . . 15 LSTTL Loads † Component q ualification in accordance with JEDEC a nd industry standards to ensure reliabl e operation over an extended temperatur e range. This includes, but is not limi ted to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cyc le, autoclave or unbiased HAST, electro migration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justif ying use of this component beyond speci fied performance and environmental limi ts. CD74HC40103ĆEP HIGHĆSPEED CMOS LOGIC 8ĆSTAGE SYNCHRONOUS DOWN COUNTER SC.
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