CD54HC4015 Shift Register Datasheet

CD54HC4015 Datasheet, PDF, Equivalent


Part Number

CD54HC4015

Description

Dual 4-Stage Static Shift Register

Manufacture

etcTI

Total Page 12 Pages
Datasheet
Download CD54HC4015 Datasheet


CD54HC4015
CD54HC4015, CD74HC4015
Data sheet acquired from Harris Semiconductor
SCHS198C
November 1997 - Revised May 2003
High Speed CMOS Logic
Dual 4-Stage Static Shift Register
[ /Title
(CD74
HC401
5)
/Sub-
ject
(High
Speed
CMOS
Logic
Dual
4-
Features
Description
• Maximum Frequency, Typically 60MHz
CL = 15pF, VCC = 5V, TA = 25oC
• Positive-Edge Clocking
• Overriding Reset
• Buffered Inputs and Outputs
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V
The ’HC4015 consists of two identical, independent, 4-stage
serial-input/parallel-output registers. Each register has
independent Clock (CP) and Reset (MR) inputs as well as a
single serial Data input. “Q” outputs are available from each
of the four stages on both registers. All register stages are D-
type, master-slave flip-flops. The logic level present at the
Data input is transferred into the first register stage and
shifted over one stage at each positive- going clock
transition. Resetting of all stages is accomplished by a high
level on the reset line.
The device can drive up to 10 low power Schottky equivalent
loads. The ’HC4015 is an enhanced version of equivalent
CMOS types.
Ordering Information
PART NUMBER
CD54HC4015F3A
CD74HC4015E
CD74HC4015M
TEMP. RANGE (oC)
-55 to 125
-55 to 125
-55 to 125
PACKAGE
16 Ld CERDIP
16 Ld PDIP
16 Ld SOIC
Pinout
CD54HC4015
(CERDIP)
CD74HC4015
(PDIP, SOIC)
TOP VIEW
2CP 1
2Q3 2
1Q2 3
1Q1 4
1Q0 5
1MR 6
1D 7
GND 8
16 VCC
15 2D
14 2MR
13 2Q0
12 2Q1
11 2Q2
10 1Q3
9 1CP
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
1

CD54HC4015
Functional Diagram
CD54HC4015, CD74HC4015
1D
1CP
1MR
7
9
6
5
1Q0
4
1Q1
3
1Q2
10
1Q3
15
2D
1
2CP
14
2MR
13
2Q0
12
2Q1
11
2Q2
2
2Q3
GND = 8
VCC = 16
TRUTH TABLE
INPUTS
OUTPUTS
CP D
l
h
X
XX
R Q0 Q1 Q2 Q3
L L q’0 q’1 q’2
L H q’0 q’1 q’2
L q’0 q’1 q’2 q’3
H L LLL
H = High Voltage Level
h = High Voltage Level One Set-up Time Prior to the Low to High Clock Transition
L = Low Voltage Level
l = Low Voltage Level One Set-up Time Prior to the Low to High Clock Transition
X = Don’t Care.
= Low to High Clock Transition
= High to Low Clock Transition
q’n = Lower case letters indicate the state of the referenced output one set-up time prior to the Low to
High clock transition.
2


Features CD54HC4015, CD74HC4015 Data sheet acqui red from Harris Semiconductor SCHS198C November 1997 - Revised May 2003 High Speed CMOS Logic Dual 4-Stage Static Sh ift Register [ /Title (CD74 HC401 5) / Subject (High Speed CMOS Logic Dual 4- Features Description • Maximum Fre quency, Typically 60MHz CL = 15pF, VCC = 5V, TA = 25oC • Positive-Edge Clock ing • Overriding Reset • Buffered I nputs and Outputs • Fanout (Over Temp erature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads • Wide Operat ing Temperature Range . . . -55oC to 12 5oC • Balanced Propagation Delay and Transition Times • Significant Power Reduction Compared to LSTTL Logic ICs • HC Types - 2V to 6V Operation - Hig h Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V The ’HC4015 consi sts of two identical, independent, 4-st age serial-input/parallel-output regist ers. Each register has independent Clock (CP) and Reset (MR) inputs as well as a sing.
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