CD54HC4017 Decade Counter/Divider Datasheet

CD54HC4017 Datasheet, PDF, Equivalent


Part Number

CD54HC4017

Description

Decade Counter/Divider

Manufacture

etcTI

Total Page 20 Pages
Datasheet
Download CD54HC4017 Datasheet


CD54HC4017
CD54HC4017, CD74HC4017
Data sheet acquired from Harris Semiconductor
SCHS200D
High-Speed CMOS Logic
November 1997 - Revised October 2003 Decade Counter/Divider with 10 Decoded Outputs
[ /Title
(CD74
HC401
7)
/Sub-
ject
(High
Speed
CMOS
Logic
Decade
Counte
Features
Description
• Fully Static Operation
• Buffered Inputs
• Common Reset
• Positive Edge Clocking
• Typical fMAX = 50MHz at VCC = 5V, CL = 15pF, TA = 25oC
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V
The ’HC4017 is a high speed silicon gate CMOS 5-stage
Johnson counter with 10 decoded outputs. Each of the
decoded outputs is normally low and sequentially goes high
on the low to high transition clock period of the 10 clock
period cycle. The CARRY (TC) output transitions low to high
after OUTPUT 10 goes from high to low, and can be used in
conjunction with the CLOCK ENABLE (CE) to cascade
several stages. The CLOCK ENABLE input disables
counting when in the high state. A RESET (MR) input is also
provided which when taken high sets all the decoded
outputs, except “0”, low.
The device can drive up to 10 low power Schottky equivalent
loads.
Ordering Information
PART NUMBER
CD54HC4017F3A
CD74HC4017E
CD74HC4017M
TEMP. RANGE
(oC)
-55 to 125
-55 to 125
-55 to 125
PACKAGE
16 Ld CERDIP
16 Ld PDIP
16 Ld SOIC
CD74HC4017MT
-55 to 125
16 Ld SOIC
CD74HC4017M96
-55 to 125
16 Ld SOIC
CD74HC4017NSR
-55 to 125
16 Ld SOP
CD74HC4017PW
-55 to 125
16 Ld TSSOP
CD74HC4017PWR
-55 to 125
16 Ld TSSOP
NOTE: When ordering, use the entire part number. The suffixes 96
and R denote tape and reel. The suffix T denotes a small-quantity
reel of 250.
Pinout
CD54HC4017 (CERDIP)
CD74HC4017 (PDIP, SOIC, SOP, TSSOP)
TOP VIEW
51
12
03
24
65
76
37
GND 8
16 VCC
15 MR
14 CP
13 CE
12 TC
11 9
10 4
98
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
1

CD54HC4017
CD54HC4017, CD74HC4017
Functional Diagram
14
CLOCK
CLOCK 13
ENABLE
MASTER 15
RESET
3
0
2
1
4
2
7
3
10
4
1
5
5
6
6
7
9
8
11
9
12 TERMINAL
COUNT
TRUTH TABLE
CP CE
LX
XH
XX
L
X
X
H
H = High Level
L = Low Level
= High to Low Transition
= Low to High Transition
X = Don’t Care.
If n < 5 TC = H, Otherwise = L
MR
L
L
H
L
L
L
L
OUTPUT STATE
No Change
No Change
“0” = H, “1”-”9” = L
Increments Counter
No Change
No Change
Increments Counter
2


Features CD54HC4017, CD74HC4017 Data sheet acqui red from Harris Semiconductor SCHS200D High-Speed CMOS Logic November 1997 - Revised October 2003 Decade Counter/Di vider with 10 Decoded Outputs [ /Title (CD74 HC401 7) /Subject (High Speed CM OS Logic Decade Counte Features Descr iption • Fully Static Operation • Buffered Inputs • Common Reset • Po sitive Edge Clocking • Typical fMAX = 50MHz at VCC = 5V, CL = 15pF, TA = 25o C • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Ou tputs . . . . . . . . . . . . . 15 LSTT L Loads • Wide Operating Temperature Range . . . -55oC to 125oC • Balanced Propagation Delay and Transition Times • Significant Power Reduction Compa red to LSTTL Logic ICs • HC Types - 2 V to 6V Operation - High Noise Immunity : NIL = 30%, NIH = 30% of VCC at VCC = 5V The ’HC4017 is a high speed silic on gate CMOS 5-stage Johnson counter wi th 10 decoded outputs. Each of the decoded outputs is normally low and sequentially goe.
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