CD74HC4017-EP DECADE COUNTER/DIVIDER Datasheet

CD74HC4017-EP Datasheet, PDF, Equivalent


Part Number

CD74HC4017-EP

Description

HIGH-SPEED CMOS LOGIC DECADE COUNTER/DIVIDER

Manufacture

etcTI

Total Page 17 Pages
Datasheet
Download CD74HC4017-EP Datasheet


CD74HC4017-EP
CD74HC4017ĆEP
HIGHĆSPEED CMOS LOGIC DECADE COUNTER/DIVIDER
WITH 10 DECODED OUTPUTS
SCLS550 − DECEMBER 2003
D Controlled Baseline
− One Assembly/Test Site, One Fabrication
Site
D Extended Temperature Performance of
−40°C to 125°C
D Enhanced Diminishing Manufacturing
Sources (DMS) Support
D Enhanced Product-Change Notification
D Qualification Pedigree
D Fully Static Operation
D Buffered Inputs
D Common Reset
D Positive Edge Clocking
D Typical fmax = 60 MHz at VCC = 5 V,
CL = 15 pF, TA = 25°C
Component qualification in accordance with JEDEC and industry
standards to ensure reliable operation over an extended
temperature range. This includes, but is not limited to, Highly
Accelerated Stress Test (HAST) or biased 85/85, temperature
cycle, autoclave or unbiased HAST, electromigration, bond
intermetallic life, and mold compound life. Such qualification
testing should not be viewed as justifying use of this component
beyond specified performance and environmental limits.
D Fanout (Over Temperature Range)
− Standard Outputs . . . 10 LSTTL Loads
− Bus Driver Outputs . . . 15 LSTTL Loads
D Balanced Propagation Delay and Transition
Times
D Significant Power Reduction Compared to
LSTTL Logic ICs
D VCC Voltage = 2 V to 6 V
D High Noise Immunity NIL or NIH = 30% of
VCC, VCC = 5 V
M OR PW PACKAGE
(TOP VIEW)
5
1
0
2
6
7
3
GND
1
2
3
4
5
6
7
8
16 VCC
15 MR
14 CP
13 CE
12 TC
11 9
10 4
98
description/ordering information
The CD74HC4017 is a high-speed silicon-gate CMOS 5-stage Johnson counter with ten decoded outputs. Each
of the decoded outputs normally is low and sequentially goes high on the low-to-high transition clock period of
the ten-clock-period cycle. The carry (TC) output transitions low to high after output 9 goes from high to low and
can be used in conjunction with the clock enable (CE) input to cascade several stages. CE disables counting
when in the high state. A master reset (MR) input also is provided that, when taken high, sets all the decoded
outputs, except output 0, to low.
The device can drive up to ten low-power Schottky equivalent loads.
ORDERING INFORMATION
TA
PACKAGE‡
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
−40°C to 125°C
SOIC − M
Tape and reel
TSSOP − PW Tape and reel
CD74HC4017QM96EP HC4017E
CD74HC4017QPWREP HC4017E
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright 2003, Texas Instruments Incorporated
1

CD74HC4017-EP
CD74HC4017ĆEP
HIGHĆSPEED CMOS LOGIC DECADE COUNTER/DIVIDER
WITH 10 DECODED OUTPUTS
SCLS550 − DECEMBER 2003
FUNCTION TABLE
INPUTS
CP CE MR
OUTPUT STATE†
LXL
No change
XHL
No change
XXH
0 = H, 1−9 = L
L L Increments counter
XL
No change
XL
No change
H L Increments counter
NOTE: H = high voltage level, L = low voltage level,
X = don’t care, = transition from low to high
level, = transition from high to low level
If n < 5, TC = H, otherwise TC = L
logic diagram (positive logic)
CP 14
13
CE
15
MR
30
21
42
73
10 4
15
56
67
98
11 9
12 TC
Decoded
Decimal
Out
2 POST OFFICE BOX 655303 DALLAS, TEXAS 75265


Features CD74HC4017ĆEP HIGHĆSPEED CMOS LOGIC DE CADE COUNTER/DIVIDER WITH 10 DECODED OU TPUTS SCLS550 − DECEMBER 2003 D Cont rolled Baseline − One Assembly/Test S ite, One Fabrication Site D Extended Te mperature Performance of −40°C to 12 5°C D Enhanced Diminishing Manufacturi ng Sources (DMS) Support D Enhanced Pro duct-Change Notification D Qualificatio n Pedigree† D Fully Static Operation D Buffered Inputs D Common Reset D Posi tive Edge Clocking D Typical fmax = 60 MHz at VCC = 5 V, CL = 15 pF, TA = 25° C † Component qualification in accord ance with JEDEC and industry standards to ensure reliable operation over an ex tended temperature range. This includes , but is not limited to, Highly Acceler ated Stress Test (HAST) or biased 85/85 , temperature cycle, autoclave or unbia sed HAST, electromigration, bond interm etallic life, and mold compound life. S uch qualification testing should not be viewed as justifying use of this compo nent beyond specified performance and environmental limits. D Fanout (Over Te.
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