CD74HC4017-Q1 DECADE COUNTER/DIVIDER Datasheet

CD74HC4017-Q1 Datasheet, PDF, Equivalent


Part Number

CD74HC4017-Q1

Description

HIGH-SPEED CMOS LOGIC DECADE COUNTER/DIVIDER

Manufacture

etcTI

Total Page 15 Pages
Datasheet
Download CD74HC4017-Q1 Datasheet


CD74HC4017-Q1
CD74HC4017-Q1
HIGH-SPEED CMOS LOGIC DECADE COUNTER/DIVIDER
WITH 10 DECODED OUTPUTS
SCLS546SA − OCTOBER 2003 − REVISED APRIL 2008
D Qualified for Automotive Applications
D Significant Power Reduction Compared to
D Fully Static Operation
D Buffered Inputs
D Common Reset
D Positive Edge Clocking
LSTTL Logic ICs
D VCC Voltage = 2 V to 6 V
D High Noise Immunity NIL or NIH = 30% of
VCC, VCC = 5 V
D Typical fMAX = 60 MHz at VCC = 5 V,
CL = 15 pF, TA = 25°C
D Fanout (Over Temperature Range)
− Standard Outputs . . . 10 LSTTL Loads
− Bus Driver Outputs . . . 15 LSTTL Loads
D Balanced Propagation Delay and Transition
Times
M OR PW PACKAGE
(TOP VIEW)
51
12
03
24
65
16 VCC
15 MR
14 CP
13 CE
12 TC
description/ordering information
76
37
11 9
10 4
The CD74HC4017 is a high-speed silicon-gate
GND 8
98
CMOS 5-stage Johnson counter with ten decoded
outputs. Each of the decoded outputs normally is low
and sequentially goes high on the low-to-high transition clock period of the ten-clock-period cycle. The carry
(TC) output transitions low to high after output 9 goes from high to low, and can be used in conjunction with the
clock enable (CE) input to cascade several stages. CE disables counting when in the high state. A master reset
(MR) input also is provided that, when taken high, sets all the decoded outputs, except output 0, to low.
The device can drive up to ten low-power Schottky equivalent loads.
ORDERING INFORMATION{
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
−40°C to 125°C
SOIC − M
Tape and reel
TSSOP − PW Tape and reel
CD74HC4017QM96Q1 HC4017Q
CD74HC4017QPWRQ1 HC4017Q
For the most current package and ordering information, see the Package Option Addendum at the
end of this document, or see the TI web site at http://www.ti.com.
Package drawings, thermal data, and symbolization are available at http://www.ti.com/packaging.
FUNCTION TABLE
INPUTS
CP CE MR
OUTPUT STATE
LXL
No change
XHL
No change
XXH
0 = H, 1−9 = L
L L Increments counter
XL
No change
XL
No change
H L Increments counter
NOTE: H = high voltage level, L = low voltage level,
X = don’t care, = transition from low to high
level, = transition from high to low level
If n < 5, TC = H, otherwise TC = L
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright 2008, Texas Instruments Incorporated
1

CD74HC4017-Q1
CD74HC4017-Q1
HIGH-SPEED CMOS LOGIC DECADE COUNTER/DIVIDER
WITH 10 DECODED OUTPUTS
SCLS546SA − OCTOBER 2003 − REVISED APRIL 2008
logic diagram (positive logic)
14
CP
13
CE
15
MR
30
21
42
73
10 4
15
56
67
98
11 9
12 TC
Decoded
Decimal
Out
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input clamp current, IIK (VI < −0.5 V or VI > VCC + 0.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < −0.5 V or VO > VCC + 0.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Source or sink current per output pin, IO (VO > −0.5 V or VO < VCC + 0.5 V) . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Package thermal impedance, θJA (see Note 2): M package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W
Maximum junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Lead temperature (during soldering):
At distance 1/16 ± 1/32 inch (1,59 ± 0,79 mm) from case for 10 s max . . . . . . . . . . . . . . . . . . . . . . . 300°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltages referenced to GND unless otherwise specified.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
2 POST OFFICE BOX 655303 DALLAS, TEXAS 75265


Features CD74HC4017-Q1 HIGH-SPEED CMOS LOGIC DECA DE COUNTER/DIVIDER WITH 10 DECODED OUTP UTS SCLS546SA − OCTOBER 2003 − REVI SED APRIL 2008 D Qualified for Automot ive Applications D Significant Power R eduction Compared to D Fully Static Op eration D Buffered Inputs D Common Rese t D Positive Edge Clocking LSTTL Logic ICs D VCC Voltage = 2 V to 6 V D High Noise Immunity NIL or NIH = 30% of VCC, VCC = 5 V D Typical fMAX = 60 MHz at VCC = 5 V, CL = 15 pF, TA = 25°C D Fan out (Over Temperature Range) − Standa rd Outputs . . . 10 LSTTL Loads − Bus Driver Outputs . . . 15 LSTTL Loads D Balanced Propagation Delay and Transiti on Times M OR PW PACKAGE (TOP VIEW) 5 1 12 03 24 65 16 VCC 15 MR 14 CP 13 CE 12 TC description/ordering informatio n 76 37 11 9 10 4 The CD74HC4017 is a high-speed silicon-gate GND 8 98 C MOS 5-stage Johnson counter with ten de coded outputs. Each of the decoded out puts normally is low and sequentially goes high on the low-to-high transition clock period of the ten-clock-pe.
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