DAC91001 Digital-to-Analog Converters Datasheet

DAC91001 Datasheet, PDF, Equivalent


Part Number

DAC91001

Description

Digital-to-Analog Converters

Manufacture

etcTI

Total Page 30 Pages
Datasheet
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DAC11001A, DAC91001, DAC81001
SLASEL0A – OCTOBER 2019 – REVISED DECEMBER 2019
DACx1001 20-Bit, 18-Bit, and 16-Bit, Low-Noise, Ultra-Low Harmonic Distortion, Fast-
Settling, High-Voltage Output, Digital-to-Analog Converters (DACs)
1 Features
1 20-bit monotonic: 1-LSB DNL (max)
• Integral linearity: 4-LSB INL (max)
• Low noise: 7nV/Hz
• Code independent low glitch:
1 nV-s
• Excellent THD: –105 dB at 1-kHz fOUT
• Fast settling: 1 µs
• Flexible output ranges: VREFPF to VREFNF
• Integrated, precision feedback resistors
• 50-MHz, 4-wire SPI-compatible interface
– Readback
– Daisy-chain
• Temperature range: –40°C to +125˚C
• Package: 48-pin TQFP
2 Applications
Lab and field instrumentation
Spectrometer
Analog output module
Battery Test
Semiconductor test
Arbitrary waveform generator (AWG)
MRI
X-ray systems
Professional audio amplifier (rack mount)
3 Description
The 20-bit DAC11001A, 18-bit DAC91001, and 16-bit
DAC81001 (DACx1001) are highly accurate, low-
noise, voltage-output, single-channel, digital-to-
analog converters (DACs). The DACx1001 are
specified monotonic by design, and offer excellent
linearity of less than 4 LSB (max) across all ranges.
The unbuffered voltage output offers low noise
performance (7 nV/Hz) in combination with a fast
settling time (1µs), making this device an excellent
choice for low-noise, fast control-loop, and waveform
generation applications. The DACx1001 integrates an
enhanced deglitch circuit with code-independent
ultra-low glitch (1 nV-s) to enable clean waveform
ramps with ultra-low total harmonic distortion (THD).
The DACx1001 devices incorporate a power-on-reset
circuit so that the DAC powers with known values in
the registers. With external references, DAC output
ranges from VREFPF to VREFNF can be achieved,
including asymmetric output ranges.
The DACx1001 use a versatile 4–wire serial interface
that operates at clock rates of up to 50 MHz. The
DACx1001 is specified over the industrial
temperature range of –40°C to +125°C.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
DAC11001
DAC91001 (preview) TQFP (48)
7.00 mm × 7.00 mm
DAC81001 (preview)
(1) For all available packages, see the package option addendum
at the end of the data sheet.
SCLK
SDIN
SYNC
SDO
LDAC
CLR
ALARM
Functional Block Diagram
IOVDD DVDD VCC AVDD REFPS REFPF
ROFS
Power On Reset
Buffer
Registers
DAC
Register
DAC
RCM
RFB
OUT
Power
Down Logic
VREFP
VREFN
High-Precision, Control-Loop Circuit
+ THS4011
± C1
± C2
+ THS4011
REFPS
REFPF
DACx1001
REFNS
REFNF
Gain/
Attenuation
±
+ THS4011
Power
Amplifier
Sensor
Output
Linear
Actuator
DGND
VSS AGND
REFNS REFNF
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.

DAC91001
DAC11001A, DAC91001, DAC81001
SLASEL0A – OCTOBER 2019 – REVISED DECEMBER 2019
www.ti.com
Table of Contents
1 Features .................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Device Comparison Table..................................... 3
6 Pin Configuration and Functions ......................... 3
7 Specifications......................................................... 5
7.1 Absolute Maximum Ratings ...................................... 5
7.2 ESD Ratings.............................................................. 5
7.3 Recommended Operating Conditions....................... 6
7.4 Thermal Information Package................................... 6
7.5 Electrical Characteristics........................................... 7
7.6 Timing Requirements: Write, 4.5 V DVDD 5.5
V............................................................................... 10
7.7 Timing Requirements: Write, 2.7 V DVDD < 4.5
V............................................................................... 11
7.8 Timing Requirements: Read and Daisy-Chain
Write, 4.5 V DVDD 5.5 V..................................... 12
7.9 Timing Requirements: Read and Daisy-Chain Write,
2.7 V DVDD < 4.5 V ............................................... 13
7.10 Typical Characteristics .......................................... 15
8 Detailed Description ............................................ 22
8.1 Overview ................................................................. 22
8.2 Functional Block Diagram ....................................... 22
8.3 Feature Description................................................. 22
8.4 Device Functional Modes........................................ 25
8.5 Programming........................................................... 26
8.6 Register Map........................................................... 28
9 Application and Implementation ........................ 33
9.1 Application Information............................................ 33
9.2 Typical Application ................................................. 33
9.3 System Examples .................................................. 38
9.4 What to Do and What Not to Do ............................ 41
9.5 Initialization Set Up ................................................ 41
10 Power Supply Recommendations ..................... 42
10.1 Power-Supply Sequencing.................................... 44
11 Layout................................................................... 45
11.1 Layout Guidelines ................................................. 45
11.2 Layout Example .................................................... 45
12 Device and Documentation Support ................. 46
12.1 Device Support...................................................... 46
12.2 Documentation Support ........................................ 46
12.3 Related Links ........................................................ 46
12.4 Receiving Notification of Documentation Updates 46
12.5 Support Resources ............................................... 46
12.6 Trademarks ........................................................... 46
12.7 Electrostatic Discharge Caution ............................ 46
12.8 Glossary ................................................................ 46
13 Mechanical, Packaging, and Orderable
Information ........................................................... 47
4 Revision History
Changes from Original (October 2019) to Revision A
Page
• Changed DAC11001A device from advanced information (preview) to production data (active) .......................................... 1
2 Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: DAC11001A DAC91001 DAC81001


Features Product Folder Order Now Technical Doc uments Tools & Software Support & Com munity DAC11001A, DAC91001, DAC81001 S LASEL0A – OCTOBER 2019 – REVISED DE CEMBER 2019 DACx1001 20-Bit, 18-Bit, an d 16-Bit, Low-Noise, Ultra-Low Harmonic Distortion, FastSettling, High-Voltage Output, Digital-to-Analog Converters ( DACs) 1 Features •1 20-bit monotonic : 1-LSB DNL (max) • Integral linearit y: 4-LSB INL (max) • Low noise: 7nV/ Hz • Code independent low glitch: 1 nV-s • Excellent THD: –105 dB at 1 -kHz fOUT • Fast settling: 1 µs • Flexible output ranges: VREFPF to VREFN F • Integrated, precision feedback re sistors • 50-MHz, 4-wire SPI-compatib le interface – Readback – Daisy-cha in • Temperature range: –40°C to + 125˚C • Package: 48-pin TQFP 2 Appli cations • Lab and field instrumentati on • Spectrometer • Analog output m odule • Battery Test • Semiconducto r test • Arbitrary waveform generator (AWG) • MRI • X-ray systems • Professional audio amplifier (rack mount) 3 Description The 20-bit DAC11001A, 18-b.
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