DAC1003D160 10-bit DAC Datasheet

DAC1003D160 Datasheet, PDF, Equivalent


Part Number

DAC1003D160

Description

Dual 10-bit DAC

Manufacture

IDT

Total Page 18 Pages
Datasheet
Download DAC1003D160 Datasheet


DAC1003D160
DAC1003D160
Dual 10 bits DAC, up to 160 MHz, 2 x interpolation
Rev. 03 — 2 July 2012
Product data sheet
1. General description
The DAC1003D160 is optimized to reduce architecture complexity and overall system
cost. The Digital-to-Analog Converter (DAC) leads dynamic performance in multi-carrier
support because of its direct IF conversion capabilities. With an internal sampling rate up
to 160 MHz, the DAC1003D160 is an extremely competitive solution for broadband
wireless systems transmitters, as well as a wide range of applications.
2. Features
Dual 10-bit resolution
Spurious Free Dynamic Range (SFDR) = 80 dBc at 2.5 MHz
Input data rate up to 80 MHz
2 interpolation filter
Output data rate up to 160 Mhz
Single 3.3 V power supply
Low noise capacitor free integrated Phase-Locked Loop (PLL)
Low power dissipation
HTQFP80 package
Ambient temperature from 40 C to +85 C
3. Applications
Broadband wireless systems
Digital radio links
Cellular base stations
Instrumentation
Cable modems
Cable Modem Termination System (CMTS)/Data Over Cable Service Interface
Specification (DOCSIS)
®

DAC1003D160
Integrated Device Technology
DAC1003D160
Dual 10 bits DAC, up to 160 MHz, 2 x interpolation
4. Ordering information
Table 1. Ordering information
Type number
Package
Name
Description
DAC1003D160HW HTQFP80 plastic thermal enhanced thin quad flat package; 80 leads;
body 12 12 1 mm; exposed die pad
5. Block diagram
Version
SOT841-1
DAC1003D160
VCCA
U/I
60 IVIRES
I9 to I0
CLK
CLKN
Q9 to Q0
11 to 16,
19 to 22
10
LATCH
10
5
CLOCK
6 DRIVER
31 to 34,
37 to 42
10
LATCH
10
DAC
FIR 10
73
72
(CLK × 2)
PLL
(CLK × 2)
INTERNAL 58
BAND GAP
(CLK × 2)
DAC
FIR 10
57
69
68
IOUT
IOUTN
GAPOUT
GAPD
QOUT
QOUTN
i.c. 2, 8
VCCD 10, 51
(1) (2) (3) (4)
VCCA
VCCA AGND DGND DEC
(1) Pins 1, 3, 61, 65, 76 and 80.
(2) Pins 4, 7, 62, 64, 66, 67, 70, 71, 74, 75, 77 and 79.
(3) Pins 9, 17, 25, 29, 30, 35, 44, 49, 50, 52, 53, 54, 55 and 56.
(4) Pins 18, 26, 36, 43, 63 and 78.
Fig 1. Block diagram
U/I 59 QVIRES
014aaa532
DAC1003D160_3
Product data sheet
Rev. 03 — 2 July 2012
© IDT 2012. All rights reserved.
2 of 18


Features DAC1003D160 Dual 10 bits DAC, up to 160 MHz, 2 x interpolation Rev. 03 — 2 July 2012 Product data sheet 1. Gener al description The DAC1003D160 is optim ized to reduce architecture complexity and overall system cost. The Digital-to -Analog Converter (DAC) leads dynamic p erformance in multi-carrier support bec ause of its direct IF conversion capabi lities. With an internal sampling rate up to 160 MHz, the DAC1003D160 is an ex tremely competitive solution for broadb and wireless systems transmitters, as w ell as a wide range of applications. 2. Features  Dual 10-bit resolution Spurious Free Dynamic Range (SFDR) = 80 dBc at 2.5 MHz  Input data rate u p to 80 MHz  2  interpolation fil ter  Output data rate up to 160 Mhz  Single 3.3 V power supply  Low n oise capacitor free integrated Phase-Lo cked Loop (PLL)  Low power dissipati on  HTQFP80 package  Ambient temp erature from 40 C to +85 C 3. Applications  Broadband wireless systems  Digital radio links  Cellular base stations  In.
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