DAC1008D650 10-bit DAC Datasheet

DAC1008D650 Datasheet, PDF, Equivalent


Part Number

DAC1008D650

Description

Dual 10-bit DAC

Manufacture

IDT

Total Page 30 Pages
Datasheet
Download DAC1008D650 Datasheet


DAC1008D650
DAC1008D650
Dual 10-bit DAC; up to 650 Msps; 2, 4or 8interpolating
with JESD204A interface
Rev. 04 — 2 July 2012
Product data sheet
1. General description
The DAC1008D650 is a high-speed 10-bit dual channel Digital-to-Analog Converter
(DAC) with selectable 2, 4or 8interpolating filters optimized for multi-carrier WCDMA
transmitters.
Because of its digital on-chip modulation, the DAC1008D650 allows the complex pattern
provided through lane 0, lane 1, lane 2 and lane 3, to be converted up from baseband to
IF. The mixing frequency is adjusted via a Serial Peripheral Interface (SPI) with a 32-bit
Numerically Controlled Oscillator (NCO) and the phase is controlled by a 16-bit register.
The DAC1008D650 also includes a 2, 4or 8clock multiplier which provides the
appropriate internal clocks and an internal regulation to adjust the output full-scale
current.
The input data format is serial according to JESD204A specification. This new interface
has numerous advantages over the traditional parallel one: easy PCB layout, lower
radiated noise, lower pin count, self-synchronous link, skew compensation. The maximum
number of lanes of the DAC1008D650 is 4 and its maximum serial data rate is
3.125 Gbps.
The Multiple Device Synchronization (MDS) guarantees a maximum skew of one output
clock period between several DAC devices. MDS incorporates modes: Master/slave and
All slave mode.
2. Features and benefits
Dual 10-bit resolution
650 Msps maximum update rate
Selectable 2, 4or 8interpolation
filters
Input data rate up to 312.5 Msps
Very low noise cap free integrated PLL
32-bit programmable NCO frequency
Four JESD204A serial input lanes
1.8 V and 3.3 V power supplies
LVDS compatible clock inputs
IMD3: 80 dBc; fs = 640 Msps;
fo = 140 MHz
ACPR: 64 dBc; two carriers WCDMA;
fs = 640 Msps; fo = 133 MHz
Typical 1.20 W power dissipation at
4interpolation, PLL off and 640 Msps
Power-down mode and Sleep modes
Differential scalable output current from
1.6 mA to 22 mA
On-chip 1.29 V reference
External analog offset control
(10-bit auxiliary DACs)
Internal digital offset control
Inverse (sin x) / x function
®

DAC1008D650
Integrated Device Technology
DAC1008D650
2, 4or 8interpolating DAC with JESD204A
Two’s complement or binary offset data Fully compatible SPI port
format
LMF = 421 or LMF = 211 support
Industrial temperature range from
40 C to +85 C
Differential CML receiver with
Integrated PLL can be bypassed
embedded termination
Synchronization of multiple DAC outputs Embedded complex modulator
3. Applications
Wireless infrastructure: LTE, WiMAX, GSM, CDMA, WCDMA, TD-SCDMA
Communication: LMDS/MMDS, point-to-point
Direct Digital Synthesis (DDS)
Broadband wireless systems
Digital radio links
Instrumentation
Automated Test Equipment (ATE)
4. Ordering information
Table 1. Ordering information
Type number
Package
Name
DAC1008D650HN
HVQFN64
Description
Version
plastic thermal enhanced very thin quad flat package; no leads; SOT804-3
64 terminals; body 9 9 0.85 mm
DAC1008D650 4
Product data sheet
Rev. 04 — 2 July 2012
© IDT 2012. All rights reserved.
2 of 96


Features DAC1008D650 Dual 10-bit DAC; up to 650 Msps; 2, 4 or 8 interpolating with JESD204A interface Rev. 04 — 2 July 2012 Product data sheet 1. Gener al description The DAC1008D650 is a hig h-speed 10-bit dual channel Digital-to- Analog Converter (DAC) with selectable 2, 4 or 8 interpolating filter s optimized for multi-carrier WCDMA tra nsmitters. Because of its digital on-ch ip modulation, the DAC1008D650 allows t he complex pattern provided through lan e 0, lane 1, lane 2 and lane 3, to be c onverted up from baseband to IF. The mi xing frequency is adjusted via a Serial Peripheral Interface (SPI) with a 32-b it Numerically Controlled Oscillator (N CO) and the phase is controlled by a 16 -bit register. The DAC1008D650 also inc ludes a 2, 4 or 8 clock multip lier which provides the appropriate int ernal clocks and an internal regulation to adjust the output full-scale curren t. The input data format is serial acco rding to JESD204A specification. This new interface has numerous advantages over th.
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