DAC1405D650 14-bit DAC Datasheet

DAC1405D650 Datasheet, PDF, Equivalent


Part Number

DAC1405D650

Description

Dual 14-bit DAC

Manufacture

IDT

Total Page 30 Pages
Datasheet
Download DAC1405D650 Datasheet


DAC1405D650
DAC1405D650
Dual 14-bit DAC, up to 650 Msps; 2, 4and 8interpolating
Rev. 05 — 2 July 2012
Product data sheet
1. General description
The DAC1405D650 is a high-speed 14-bit dual channel Digital-to-Analog Converter
(DAC) with selectable 2, 4or 8interpolating filters optimized for multi-carrier wireless
transmitters.
Thanks to its digital on-chip modulation, the DAC1405D650 allows the complex I and Q
inputs to be converted up from baseband to IF. The mixing frequency is adjusted via a
Serial Peripheral Interface (SPI) with a 32-bit Numerically Controlled Oscillator (NCO) and
the phase is controlled by a 16-bit register.
Two modes of operation are available: separate data ports or a single interleaved
high-speed data port. In the Interleaved mode, the input data stream is demultiplexed into
its original I and Q data and then latched.
The DAC1405D650 also includes a 2, 4and 8clock multiplier which provides the
appropriate internal clocks and an internal regulator to adjust the output full-scale current.
2. Features and benefits
Dual 14-bit resolution
650 Msps maximum update rate
IMD3: 80 dBc; fs = 640 Msps; fo = 96 MHz
ACPR: 71 dBc; 2 carriers WCDMA;
fs = 614.4 Msps; fo = 96 MHz; PLL on
Selectable 2, 4or 8interpolation Typical 0.95 W power dissipation at 4
filters
interpolation
Input data rate up to 160 Msps
Power-down and Sleep modes
Very low noise cap-free integrated PLL Differential scalable output current from
1.6 mA to 22 mA
32-bit programmable NCO frequency On-chip 1.29 V reference
Dual port or Interleaved data modes External analog offset control
(10-bit auxiliary DACs)
1.8 V and 3.3 V power supplies
Internal digital offset control
LVDS compatible clock
Inverse (sin x) / x function
Two’s complement or binary offset Fully compatible SPI port
data format
3.3 V CMOS input buffers
Industrial temperature range from
40 C to +85 C
®

DAC1405D650
Integrated Device Technology
DAC1405D650
Dual 14-bit DAC, up to 650 Msps; 2, 4and 8interpolating
3. Applications
Wireless infrastructure: LTE, WiMAX, GSM, CDMA, WCDMA, TD-SCDMA
Communication: LMDS/MMDS, point-to-point
Direct Digital Synthesis (DDS)
Broadband wireless systems
Digital radio links
Instrumentation
Automated Test Equipment (ATE)
4. Ordering information
Table 1. Ordering information
Type number
Package
Name
DAC1405D650HW
HTQFP100
Description
plastic thermal enhanced thin quad flat package; 100 leads;
body 14 14 1 mm; exposed die pad
Version
SOT638-1
DAC1405D650 5
Product data sheet
Rev. 05 — 2 July 2012
© IDT 2012. All rights reserved.
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Features DAC1405D650 Dual 14-bit DAC, up to 650 Msps; 2, 4 and 8 interpolating Rev. 05 — 2 July 2012 Product data sheet 1. General description The DAC1 405D650 is a high-speed 14-bit dual cha nnel Digital-to-Analog Converter (DAC) with selectable 2, 4 or 8 inte rpolating filters optimized for multi-c arrier wireless transmitters. Thanks to its digital on-chip modulation, the DA C1405D650 allows the complex I and Q in puts to be converted up from baseband t o IF. The mixing frequency is adjusted via a Serial Peripheral Interface (SPI) with a 32-bit Numerically Controlled O scillator (NCO) and the phase is contro lled by a 16-bit register. Two modes of operation are available: separate data ports or a single interleaved high-spe ed data port. In the Interleaved mode, the input data stream is demultiplexed into its original I and Q data and then latched. The DAC1405D650 also includes a 2, 4 and 8 clock multiplier which provides the appropriate internal clocks and an internal regulator to adjust.
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