DAC1405D750 14-bit DAC Datasheet

DAC1405D750 Datasheet, PDF, Equivalent


Part Number

DAC1405D750

Description

Dual 14-bit DAC

Manufacture

IDT

Total Page 30 Pages
Datasheet
Download DAC1405D750 Datasheet


DAC1405D750
DAC1405D750
Dual 14-bit DAC, up to 750 Msps; 4x and 8x interpolating
Rev. 06 — 2 July 2012
Product data sheet
1. General description
The DAC1405D750 is a high-speed 14-bit dual channel Digital-to-Analog Converter
(DAC) with selectable 4or 8interpolating filters optimized for multi-carrier wireless
transmitters.
Thanks to its digital on-chip modulation, the DAC1405D750 allows the complex I and Q
inputs to be converted from BaseBand (BB) to IF. The mixing frequency is adjusted via a
Serial Peripheral Interface (SPI) with a 32-bit Numerically Controlled Oscillator (NCO) and
the phase is controlled by a 16-bit register.
Two modes of operation are available: separate data ports or a single interleaved
high-speed data port. In the Interleaved mode, the input data stream is demultiplexed into
its original I and Q data and then latched.
A 4and 8clock multiplier enables the DAC1405D750 to provide the appropriate
internal clocks from the internal PLL. The internal PLL can be bypassed enabling the use
of an external high frequency clock. The voltage regulator enables adjustment of the
output full-scale current.
2. Features and benefits
Dual 14-bit resolution
750 Msps maximum update rate
IMD3: 74 dBc; fs = 737.28 Msps;
fo = 140 MHz
ACPR: 72 dBc; 2-carrier WCDMA;
fs = 737.28 Msps; fo = 153.6 MHz
Selectable 4or 8interpolation filters Typical 1.2 W power dissipation at 4
interpolation, PLL off and 740 Msps
Input data rate up to 185 Msps
Power-down and Sleep modes
Very low noise cap-free integrated PLL Differential scalable output current from
1.6 mA to 22 mA
32-bit programmable NCO frequency On-chip 1.29 V reference
Dual port or Interleaved data modes External analog offset control
(10-bit auxiliary DACs)
1.8 V and 3.3 V power supplies
Internal digital offset control
LVDS compatible clock
Inverse x / (sin x) function
Two’s complement or binary offset Fully compatible SPI port
data format
1.8 V/3.3 V CMOS input data buffers Industrial temperature range from
40 C to +85 C
®

DAC1405D750
Integrated Device Technology
DAC1405D750
Dual 14-bit DAC, up to 750 Msps; 4and 8interpolating
3. Applications
Wireless infrastructure: LTE, WiMAX, GSM, CDMA, WCDMA, TD-SCDMA
Communication: LMDS/MMDS, point-to-point
Direct Digital Synthesis (DDS)
Broadband wireless systems
Digital radio links
Instrumentation
Automated Test Equipment (ATE)
4. Ordering information
Table 1. Ordering information
Type number
Package
Name
DAC1405D750HW
HTQFP100
Description
plastic thermal enhanced thin quad flat package; 100 leads;
body 14 14 1 mm; exposed die pad
Version
SOT638-1
DAC1405D750 6
Product data sheet
Rev. 06 — 2 July 2012
© IDT 2012. All rights reserved.
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Features DAC1405D750 Dual 14-bit DAC, up to 750 Msps; 4x and 8x interpolating Rev. 06 — 2 July 2012 Product data sheet 1. General description The DAC1405D750 is a high-speed 14-bit dual channel Digit al-to-Analog Converter (DAC) with selec table 4 or 8 interpolating filter s optimized for multi-carrier wireless transmitters. Thanks to its digital on- chip modulation, the DAC1405D750 allows the complex I and Q inputs to be conve rted from BaseBand (BB) to IF. The mixi ng frequency is adjusted via a Serial P eripheral Interface (SPI) with a 32-bit Numerically Controlled Oscillator (NCO ) and the phase is controlled by a 16-b it register. Two modes of operation are available: separate data ports or a si ngle interleaved high-speed data port. In the Interleaved mode, the input data stream is demultiplexed into its origi nal I and Q data and then latched. A 4 and 8 clock multiplier enables th e DAC1405D750 to provide the appropriat e internal clocks from the internal PLL. The internal PLL can be bypassed.
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