DAC1627D1G25 16-bit DAC Datasheet

DAC1627D1G25 Datasheet, PDF, Equivalent


Part Number

DAC1627D1G25

Description

Dual 16-bit DAC

Manufacture

IDT

Total Page 30 Pages
Datasheet
Download DAC1627D1G25 Datasheet


DAC1627D1G25
DAC1627D1G25
Dual 16-bit DAC, LVDS interface, up to 1.25 Gsps, x2, x4 and
x8 interpolating
Rev. 4.00 — 12 December 2012
Product data sheet
1. General description
The DAC1627D1G25 is a high-speed 16-bit dual channel Digital-to-Analog Converter
(DAC). It incorporates selectable ×2, ×4 and ×8 interpolation filters optimized for
multi-carrier and broadband wireless transmitters at sample rates of up to 1.25 Gsps. The
DAC1627D1G25 is supplied by two power supplies and integrates a differential scalable
output current up to 34 mA.
The DAC1627D1G25 meets multi-carrier Global System for Mobile communications
(GSM) specifications. For example, with an NCO frequency of 153.6 MHz and a DAC
clock frequency of 1.2288 Gsps the full-scale dynamic range is:
SFDRRBW = 90 dBc (bandwidth = 180 MHz)
IMD3 = 85 dBc
The Serial Peripheral Interface (SPI) provides full control of the DAC1627D1G25.
The DAC1627D1G25 integrates a Low Voltage Differential Signaling (LVDS) Double Data
Rate (DDR) receiver interface, with an on-chip 100 termination. The LVDS DDR
interface accepts a multiplex input data stream such as interleaved or folded. An internal
LVDS input auto-calibration ensures the robustness and stability of the interface.
Digital on-chip modulation converts the complex I and Q inputs from baseband to IF. A
40-bit Numerically Controlled Oscillator (NCO) sets the mixer frequency. High resolution
internal gain, phase and offset control provide outstanding image and Local Oscillator
(LO) signal rejection at the system analog modulator output.
An inverse (sin x) / x function ensures a controlled flatness 0.5 dB for high bandwidths at
the DAC output.
Multiple Device Synchronization (MDS) allows synchronization of the outputs of multiple
DAC devices. MDS guarantees a maximum skew of one output clock period between
several devices.
The DAC1627D1G25 includes a low noise capacitor-free integrated Phase-Locked Loop
(PLL) multiplier which generates a DAC clock rate from the LVDS clock rate.
The DAC1627D1G25 is available in an HVQFN72 package (10 mm × 10 mm).
®

DAC1627D1G25
Integrated Device Technology
DAC1627D1G25
Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating
2. Features and benefits
Dual-channel 16-bit resolution
1.25 Gsps maximum update rate
Selectable ×2, ×4 and ×8 interpolation
filters
Low noise capacitor-free integrated
Phase-Locked Loop (PLL)
Embedded Numerically Controlled
Oscillator (NCO) with 40-bit
programmable frequency
Embedded complex (I/Q) modulator
Two power supplies
LVDS DDR compatible input interface
with on-chip 100 terminations
LVDS DDR input clock up to 400 MHz
LVDS or LVPECL compatible DAC clock
Interleaved or folded I and Q data input
mode
Synchronization of multiple DAC
devices
3-wire or 4-wire mode SPI interface
Differential scalable output current from
8.1 mA to 34 mA
External analog offset control
(10-bit auxiliary DACs)
High resolution internal digital gain and
offset control to support high
performance IQ-modulator image
rejection
Internal phase correction
Inverse (sin x) / x function
Power-down mode and Sleep mode;
5-bit NCO low-power mode
On-chip 1.25 V reference
Industrial temperature range 40 °C to
+85 °C
72 pins small form factor HVQFN
package
3. Applications
Wireless infrastructure: MC_GSM, LTE, WiMAX, GSM, CDMA, WCDMA, TD-SCDMA
Communications: LMDS/MMDS, point-to-point
Direct Digital Synthesis (DDS)
Digital radio links
Instrumentation
Automated Test Equipment (ATE)
4. Ordering information
Table 1. Ordering information
Type number
Package
Name
Description
DAC1627D1G25 HVQFN72 plastic thermal enhanced very thin quad flat package; no leads;
72 terminals; body 10 × 10 × 0.85 mm
Version
SOT813-3
DAC1627D1G25
Product data sheet
Rev. 4 — 12 December 2012
© IDT 2012. All rights reserved.
2 of 81


Features DAC1627D1G25 Dual 16-bit DAC, LVDS inte rface, up to 1.25 Gsps, x2, x4 and x8 i nterpolating Rev. 4.00 — 12 December 2012 Product data sheet 1. General d escription The DAC1627D1G25 is a high-s peed 16-bit dual channel Digital-to-Ana log Converter (DAC). It incorporates se lectable ×2, ×4 and ×8 interpolation filters optimized for multi-carrier an d broadband wireless transmitters at sa mple rates of up to 1.25 Gsps. The DAC1 627D1G25 is supplied by two power suppl ies and integrates a differential scala ble output current up to 34 mA. The DAC 1627D1G25 meets multi-carrier Global Sy stem for Mobile communications (GSM) sp ecifications. For example, with an NCO frequency of 153.6 MHz and a DAC clock frequency of 1.2288 Gsps the full-scale dynamic range is: • SFDRRBW = 90 dBc (bandwidth = 180 MHz) • IMD3 = 85 dB c The Serial Peripheral Interface (SPI) provides full control of the DAC1627D1 G25. The DAC1627D1G25 integrates a Low Voltage Differential Signaling (LVDS) Double Data Rate (DDR) receiver in.
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