DRV8320 Gate Driver Datasheet

DRV8320 Datasheet, PDF, Equivalent


Part Number

DRV8320

Description

6 to 60-V Three-Phase Smart Gate Driver

Manufacture

etcTI

Total Page 30 Pages
Datasheet
Download DRV8320 Datasheet


DRV8320
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DRV8320, DRV8320R
DRV8323, DRV8323R
SLVSDJ3C – FEBRUARY 2017 – REVISED AUGUST 2018
DRV832x 6 to 60-V Three-Phase Smart Gate Driver
1 Features
1 Triple Half-Bridge Gate Driver
– Drives 3 High-Side and 3 Low-Side N-Channel
MOSFETs (NMOS)
• Smart Gate Drive Architecture
– Adjustable Slew Rate Control
– 10-mA to 1-A Peak Source Current
– 20-mA to 2-A Peak Sink Current
• Integrated Gate Driver Power Supplies
– Supports 100% PWM Duty Cycle
– High-Side Charge Pump
– Low-Side Linear Regulator
• 6 to 60-V Operating Voltage Range
• Optional Integrated Buck Regulator
LMR16006X SIMPLE SWITCHER®
– 4 to 60-V Operating Voltage Range
– 0.8 to 60-V, 600-mA Output Capability
• Optional Integrated Triple Current Sense
Amplifiers (CSAs)
– Adjustable Gain (5, 10, 20, 40 V/V)
– Bidirectional or Unidirectional Support
• SPI and Hardware Interface Available
• 6x, 3x, 1x, and Independent PWM Modes
• Supports 1.8-V, 3.3-V, and 5-V Logic Inputs
• Low-Power Sleep Mode (12 µA)
• Linear Voltage Regulator, 3.3 V, 30 mA
• Compact QFN Packages and Footprints
• Efficient System Design With Power Blocks
• Integrated Protection Features
– VM Undervoltage Lockout (UVLO)
– Charge Pump Undervoltage (CPUV)
– MOSFET Overcurrent Protection (OCP)
– Gate Driver Fault (GDF)
– Thermal Warning and Shutdown (OTW/OTSD)
– Fault Condition Indicator (nFAULT)
2 Applications
• Brushless-DC (BLDC) Motor Modules and PMSM
• Fans, Pumps, and Servo Drives
• E-Bikes, E-Scooters, and E-Mobility
• Cordless Garden and Power Tools, Lawnmowers
• Cordless Vacuum Cleaners
• Drones, Robotics, and RC Toys
• Industrial and Logistics Robots
1
3 Description
The DRV832x family of devices is an integrated gate
driver for three-phase applications. The devices
provide three half-bridge gate drivers, each capable
of driving high-side and low-side N-channel power
MOSFETs. The DRV832x generates the correct gate
drive voltages using an integrated charge pump for
the high-side MOSFETs and a linear regulator for the
low-side MOSFETs. The Smart Gate Drive
architecture supports peak gate drive currents up to
1-A source and 2-A. The DRV832x can operate from
a single power supply and supports a wide input
supply range of 6 to 60 V for the gate driver and 4 to
60 V for the optional buck regulator.
The 6x, 3x, 1x, and independent input PWM modes
allow for simple interfacing to controller circuits. The
configuration settings for the gate driver and device
are highly configurable through the SPI or hardware
(H/W) interface. The DRV8323 and DRV8323R
devices integrate three low-side current sense
amplifiers that allow bidirectional current sensing on
all three phases of the drive stage. The DRV8320R
and DRV8323R devices integrate a 600-mA buck
regulator.
A low-power sleep mode is provided to achieve low
quiescent current draw by shutting down most of the
internal circuitry. Internal protection functions are
provided for undervoltage lockout, charge pump fault,
MOSFET overcurrent, MOSFET short circuit, gate
driver fault, and overtemperature. Fault conditions are
indicated on the nFAULT pin with details through the
device registers for SPI device variants.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
DRV8320
WQFN (32)
5.00 mm × 5.00 mm
DRV8320R
VQFN (40)
6.00 mm × 6.00 mm
DRV8323
WQFN (40)
6.00 mm × 6.00 mm
DRV8323R
VQFN (48)
7.00 mm × 7.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
6 to 60 V
PWM
SPI or H/W
nFAULT
Current Sense
600 mA
DRV832x
Three-Phase
Smart Gate Driver
Gate Drive
M
Protection
3x Sense Amplifiers
(DRV8323 only)
Buck Regulator
Current
Sense
Copyright © 201 7, Texas Instrumen ts Incorpor ate d
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.

DRV8320
DRV8320, DRV8320R
DRV8323, DRV8323R
SLVSDJ3C – FEBRUARY 2017 – REVISED AUGUST 2018
www.ti.com
Table of Contents
1 Features .................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Device Comparison Table..................................... 4
6 Pin Configuration and Functions ......................... 4
7 Specifications....................................................... 11
7.1 Absolute Maximum Ratings .................................... 11
7.2 ESD Ratings .......................................................... 11
7.3 Recommended Operating Conditions..................... 12
7.4 Thermal Information ................................................ 12
7.5 Electrical Characteristics......................................... 13
7.6 SPI Timing Requirements ....................................... 18
7.7 Typical Characteristics ............................................ 19
8 Detailed Description ............................................ 21
8.1 Overview ................................................................. 21
8.2 Functional Block Diagram ....................................... 22
8.3 Feature Description................................................. 30
8.4 Device Functional Modes........................................ 50
8.5 Programming........................................................... 51
8.6 Register Maps ......................................................... 53
9 Application and Implementation ........................ 61
9.1 Application Information............................................ 61
9.2 Typical Application ................................................. 61
10 Power Supply Recommendations ..................... 70
10.1 Bulk Capacitance Sizing ....................................... 70
11 Layout................................................................... 71
11.1 Layout Guidelines ................................................. 71
11.2 Layout Example .................................................... 72
12 Device and Documentation Support ................. 73
12.1 Device Support...................................................... 73
12.2 Documentation Support ........................................ 73
12.3 Related Links ........................................................ 73
12.4 Receiving Notification of Documentation Updates 74
12.5 Community Resources.......................................... 74
12.6 Trademarks ........................................................... 74
12.7 Electrostatic Discharge Caution ............................ 74
12.8 Glossary ................................................................ 74
13 Mechanical, Packaging, and Orderable
Information ........................................................... 74
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (December 2017) to Revision C
Page
• Changed the Applications....................................................................................................................................................... 1
• Updated input labels for the INLx and INHx signals in the Layout Example imags ............................................................. 72
• Added the DRV835x device options to the image in the Device Nomenclature section...................................................... 73
Changes from Revision A (April 2017) to Revision B
Page
• Changed the low-power sleep mode supply current from the maximum value (20 µA) to the typical value (12 µA) in
the Features............................................................................................................................................................................ 1
• Changed the Applications....................................................................................................................................................... 1
• Changed the GAIN value from 45 kΩ to 47 kΩ in the test condition of the amplifier gain for the H/W device in the
Electrical Characteristics table ............................................................................................................................................. 15
• Deleted tEN_nSCS from the SPI Slave Mode Timing Diagram................................................................................................. 18
• Added a note to the Synchronous 1x PWM Mode to define !PWM ..................................................................................... 31
• Updated the Auto Offset Calibration section ........................................................................................................................ 44
• Updated the VDS Latched Shutdown and VDS Automatic Retry sections ............................................................................. 48
• Updated the Sleep Mode section ......................................................................................................................................... 50
• Changed the address listed in the title for the Gate Drive LS Register section to the correct register address, 0x04 ........ 58
• Changed the maximum Qg value for both trapezoidal and sinusoidal commutation the VVM = 8 V example of the
Detailed Design Procedure................................................................................................................................................... 63
• Changed IDRIVEP and IDRIVEN equations in the IDRIVE Configuration section ....................................................................... 64
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Copyright © 2017–2018, Texas Instruments Incorporated
Product Folder Links: DRV8320 DRV8320R DRV8323 DRV8323R


Features Product Folder Order Now Technical Doc uments Tools & Software Support & Com munity Reference Design DRV8320, DRV8 320R DRV8323, DRV8323R SLVSDJ3C – FEB RUARY 2017 – REVISED AUGUST 2018 DRV8 32x 6 to 60-V Three-Phase Smart Gate Dr iver 1 Features •1 Triple Half-Bridg e Gate Driver – Drives 3 High-Side an d 3 Low-Side N-Channel MOSFETs (NMOS) Smart Gate Drive Architecture – Ad justable Slew Rate Control – 10-mA to 1-A Peak Source Current – 20-mA to 2 -A Peak Sink Current • Integrated Gat e Driver Power Supplies – Supports 10 0% PWM Duty Cycle – High-Side Charge Pump – Low-Side Linear Regulator • 6 to 60-V Operating Voltage Range • O ptional Integrated Buck Regulator – L MR16006X SIMPLE SWITCHER® – 4 to 60- V Operating Voltage Range – 0.8 to 60 -V, 600-mA Output Capability • Option al Integrated Triple Current Sense Ampl ifiers (CSAs) – Adjustable Gain (5, 1 0, 20, 40 V/V) – Bidirectional or Uni directional Support • SPI and Hardware Interface Available • 6x, 3x, 1x, and Independent PWM Modes • Sup.
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