STM32H7A3LG 280MHz MCU Datasheet

STM32H7A3LG Datasheet, PDF, Equivalent


Part Number

STM32H7A3LG

Description

32-bit Arm Cortex-M7 280MHz MCU

Manufacture

STMicroelectronics

Total Page 30 Pages
Datasheet
Download STM32H7A3LG Datasheet


STM32H7A3LG
STM32H7A3xI/G
Datasheet
32-bit Arm® Cortex®-M7 280 MHz MCUs, up to 2-Mbyte Flash memory, 1.4
Mbyte RAM, 46 com. and analog interfaces, SMPS
FBGA
LQFP64
(10 x 10 mm)
LQFP100
(14 x 14 mm)
LQFP144
(20x20 mm)
LQFP176
(24 x 24 mm)
FBGA
TFBGA100
(8 x 8 mm)
TFBGA216
(13x13 mm)
TFBGA225
(13x13 mm)
UFBGA169
(7 x 7 mm)
UFBGA176+25
(10x10 mm)
WLCSP132
(4.57 X 4.37 mm)
Product summary
STM32H7A3xI
STM32H7A3RI,
STM32H7A3VI,
STM32H7A3QI,
STM32H7A3ZI,
STM32H7A3AI,
STM32H7A3II,
STM32H7A3NI,
STM32H7A3LI
STM32H7A3xG
STM32H7A3RG,
STM32H7A3VG,
STM32H7A3ZG,
STM32H7A3AG,
STM32H7A3IG,
STM32H7A3NG,
STM32H7A3LG
Features
Core
• 32-bit Arm® Cortex®-M7 core with double-precision FPU and L1 cache:
16 Kbytes of data and 16 Kbytes of instruction cache allowing to fill one cache
line in a single access from the 128-bit embedded Flash memory; frequency up
to 280 MHz, MPU, 599 DMIPS/ 2.14 DMIPS/MHz (Dhrystone 2.1), and DSP
instructions
Memories
• Up to 2 Mbytes of Flash memory with read while write support, plus 1 Kbyte of
OTP memory
• ~1.4 Mbytes of RAM: 192 Kbytes of TCM RAM (inc. 64 Kbytes of ITCM RAM +
128 Kbytes of DTCM RAM for time critical routines), 1.18 Mbytes of user SRAM,
and 4 Kbytes of SRAM in Backup domain
• 2x Octo-SPI memory interfaces, I/O multiplexing and support for serial PSRAM/
NAND/NOR, Hyper RAM/Flash frame formats, running up to 140 MHz in SRD
mode and up to 110 MHz in DTR mode
• Flexible external memory controller with up to 32-bit data bus:
– SRAM, PSRAM, NOR Flash memory clocked up to 125 MHz in
Synchronous mode
– SDRAM/LPSDR SDRAM
– 8/16-bit NAND Flash memories
• CRC calculation unit
Security
• ROP, PC-ROP, active tamper, secure firmware upgrade support
General-purpose input/outputs
• Up to 168 I/O ports with interrupt capability
– Fast I/Os capable of up to 133 MHz
– Up to 164 5-V-tolerant I/Os
Low-power consumption
• Stop: down to 32 µA with full RAM retention
• Standby: 2.8 µA (Backup SRAM OFF, RTC/LSE ON, PDR OFF)
• VBAT: 0.8 µA (RTC and LSE ON)
Clock management
• Internal oscillators: 64 MHz HSI, 48 MHz HSI48, 4 MHz CSI, 32 kHz LSI
• External oscillators: 4-50 MHz HSE, 32.768 kHz LSE
• 3× PLLs (1 for the system clock, 2 for kernel clocks) with fractional mode
DS13195 - Rev 1 - January 2020
For further information contact your local STMicroelectronics sales office.
www.st.com

STM32H7A3LG
DS13195 - Rev 1
STM32H7A3xI/G
Reset and power management
• 2 separate power domains, which can be independently clock gated to maximize
power efficiency:
– CPU domain (CD) for Arm® Cortex® core and its peripherals, which can be
independently switched in Retention mode
– Smart run domain (SRD) for reset and clock control, power management
and some peripherals
• 1.62 to 3.6 V application supply and I/Os
• POR, PDR, PVD and BOR
• Dedicated USB power embedding a 3.3 V internal regulator to supply the
internal PHYs
• Dedicated SDMMC power supply
• High power efficiency SMPS step-down converter regulator to directly supply
VCORE or an external circuitry
• Embedded regulator (LDO) with configurable scalable output to supply the
digital circuitry
• Voltage scaling in Run and Stop mode
• Backup regulator (~0.9 V)
• Low-power modes: Sleep, Stop and Standby
• VBAT battery operating mode with charging capability
• CPU and domain power state monitoring pins
Interconnect matrix
• 3 bus matrices (1 AXI and 2 AHB)
• Bridges (5× AHB2APB, 3× AXI2AHB)
5 DMA controllers to unload the CPU
• 1× high-speed general-purpose master direct memory access controller
(MDMA)
• 2× dual-port DMAs with FIFO and request router capabilities
• 1× basic DMA with request router capabilities
• 1x basic DMA dedicated to DFSDM
Up to 35 communication peripherals
• 4× I2C FM+ interfaces (SMBus/PMBus)
• 5× USART/5x UARTs (ISO7816 interface, LIN, IrDA, modem control) and 1x
LPUART
• 6× SPIs, including 4 with muxed full-duplex I2S audio class accuracy via internal
audio PLL or external clock and 1 x SPI/I2S in LP domain (up to 125 MHz)
• 2x SAIs (serial audio interface)
• SPDIFRX interface
• SWPMI single-wire protocol master interface
• MDIO Slave interface
• 2× SD/SDIO/MMC interfaces (up to 133 MHz)
• 2× CAN controllers: 2 with CAN FD, 1 with time-triggered CAN (TT-CAN)
• 1× USB OTG interfaces (1HS/FS)
• HDMI-CEC
• 8- to 14-bit camera interface up to 80 MHz
• 8-/16-bit parallel synchronous data input/output slave interface (PSSI)
page 2/226


Features STM32H7A3xI/G Datasheet 32-bit Arm® Cor tex®-M7 280 MHz MCUs, up to 2-Mbyte Fl ash memory, 1.4 Mbyte RAM, 46 com. and analog interfaces, SMPS FBGA LQFP64 ( 10 x 10 mm) LQFP100 (14 x 14 mm) LQFP14 4 (20x20 mm) LQFP176 (24 x 24 mm) FBGA TFBGA100 (8 x 8 mm) TFBGA216 (13x13 mm ) TFBGA225 (13x13 mm) UFBGA169 (7 x 7 mm) UFBGA176+25 (10x10 mm) WLCSP132 (4 .57 X 4.37 mm) Product summary STM32H 7A3xI STM32H7A3RI, STM32H7A3VI, STM32H 7A3QI, STM32H7A3ZI, STM32H7A3AI, STM32H 7A3II, STM32H7A3NI, STM32H7A3LI STM32H 7A3xG STM32H7A3RG, STM32H7A3VG, STM32H 7A3ZG, STM32H7A3AG, STM32H7A3IG, STM32H 7A3NG, STM32H7A3LG Features Core • 3 2-bit Arm® Cortex®-M7 core with doubl e-precision FPU and L1 cache: 16 Kbytes of data and 16 Kbytes of instruction c ache allowing to fill one cache line in a single access from the 128-bit embed ded Flash memory; frequency up to 280 M Hz, MPU, 599 DMIPS/ 2.14 DMIPS/MHz (Dhr ystone 2.1), and DSP instructions Memor ies • Up to 2 Mbytes of Flash memory with read while write support, p.
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