NDP6020P / NDB6020P P-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description
Features
These...
NDP6020P / NDB6020P P-Channel Logic Level Enhancement Mode Field Effect
Transistor
General Description
Features
These logic level P-Channel enhancement mode power field effect
transistors are produced using ON Semiconductor's proprietary, high cell density, DMOS technology. This very high density process has been especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulses in the avalanche and commutation modes. These devices are particularly suited for low voltage applications such as automotive, DC/DC converters, PWM motor controls, and other battery powered circuits where fast switching, low in-line power loss, and resistance to transients are needed.
-24
A,
-20
V.
RDS(ON) RDS(ON) RDS(ON)
= = =
000...0007755ΩΩΩ@@@VVGVGSGS==S=-2-4-.27.5.5VV.V. .
Critical DC electrical parameters specified at elevated temperature.
Rugged internal source-drain diode can eliminate the need for an external Zener diode transient suppressor.
175°C maximum junction temperature rating.
High density cell design for extremely low RDS(ON).
TO-220 and TO-263 (D2PAK) package for both through hole and surface mount applications.
________________________________________________________________________________
S
G
D
Absolute Maximum Ratings TC = 25°C unless otherwise noted
Symbol Parameter
NDP6020P
VDSS Drain-Source Voltage VGSS Gate-Source Voltage - Continuous ID Drain Current - Continuous
- Pulsed
PD Total Power Dissi...