FDC6320C Digital FET Datasheet

FDC6320C Datasheet, PDF, Equivalent


Part Number

FDC6320C

Description

Dual N & P Channel Digital FET

Manufacture

ON Semiconductor

Total Page 8 Pages
Datasheet
Download FDC6320C Datasheet


FDC6320C
FDC6320C
Dual N & P Channel , Digital FET
General Description
These dual N & P Channel logic level enhancement mode
field effect transistors are produced using ON
Semiconductor's proprietary, high cell density, DMOS
technology. This very high density process is especially
tailored to minimize on-state resistance. The device is an
improved design especially for low voltage applications as a
replacement for bipolar digital transistors in load switching
applications. Since bias resistors are not required, this dual
digital FET can replace several digital transistors with
difference bias resistors.
Features
N-Ch 25 V, 0.22 A, RDS(ON) = 5 @ VGS= 2.7 V.
P-Ch 25 V, -0.12 A, RDS(ON) = 13 @ VGS= -2.7 V.
Very low level gate drive requirements allowing direct
operation in 3 V circuits. VGS(th) < 1.5 V.
Gate-Source Zener for ESD ruggedness.
>6kV Human Body Model
Replace NPN & PNP digital transistors.
SOT-23
SuperSOTTM-6
SuperSOTTM-8
SO-8
SOT-223
SOIC-16
43
52
61
Absolute Maximum Ratings TA = 25oC unless other wise noted
Symbol Parameter
N-Channel
VDSS, VCC
VGSS, VIN
ID, IO
Drain-Source Voltage, Power Supply Voltage
Gate-Source Voltage,
Drain/Output Current - Continuous
- Pulsed
25
8
0.22
0.5
PD Maximum Power Dissipation
(Note 1a)
(Note 1b)
TJ,TSTG
ESD
Operating and Storage Tempature Ranger
Electrostatic Discharge Rating MIL-STD-883D
Human Body Model (100pf / 1500 Ohm)
THERMAL CHARACTERISTICS
RθJA
Thermal Resistance, Junction-to-Ambient (Note 1a)
RθJC Thermal Resistance, Junction-to-Case (Note 1)
0.9
0.7
-55 to 150
6
140
60
P-Channel
-25
-8
-0.12
-0.5
Units
V
V
A
W
°C
kV
°C/W
°C/W
© 1997 Semiconductor Components Industries, LLC.
October-2017, Rev. 3
Publication Order Number:
FDC6320C/D

FDC6320C
DMOS Electrical Characteristics (TA = 25 OC unless otherwise noted )
Symbol
Parameter
Conditions
OFF CHARACTERISTICS
BVDSS
Drain-Source Breakdown Voltage
BVDSS/TJ Breakdown Voltage Temp. Coefficient
IDSS Zero Gate Voltage Drain Current
IDSS Zero Gate Voltage Drain Current
IGSS Gate - Body Leakage Current
ON CHARACTERISTICS (Note 2)
VGS(th)/TJ Gate Threshold Voltage Temp. Coefficient
VGS(th)
Gate Threshold Voltage
RDS(ON)
Static Drain-Source On-Resistance
ID(ON) On-State Drain Current
gFS Forward Transconductance
DYNAMIC CHARACTERISTICS
Ciss Input Capacitance
Coss Output Capacitance
Crss Reverse Transfer Capacitance
VGS = 0 V, ID = 250 µA
VGS = 0 V, ID = -250 µA
ID= 250 µA, Referenced to 25 oC
ID = -250 µA, Referenced to 25 oC
VDS= 20 V, VGS= 0 V,
TJ = 55°C
VDS =-20 V, VGS = 0 V,
TJ = 55°C
VGS = 8 V, VDS= 0 V
VGS = -8 V, VDS= 0 V
ID = 250 µA, Referenced to 25 o C
ID= -250 µA, Referenced to 25 o C
VDS = VGS, ID= 250 µA
VDS = VGS, ID= -250 µA
VGS = 2.7 V, ID = 0.2 A
TJ =125°C
VGS = 4.5 V, ID = 0.4 A
VGS = -2.7 V, ID = -0.05 A
TJ =125°C
VGS = -4.5 V, ID = -0.2 A
VGS = 2.7 V, VDS = 5 V
VGS = -2.7 V, VDS = -5 V
VDS = 5 V, ID= 0.4 A
VDS = -5 V, ID= -0.2 A
N-Channel
VDS = 10 V, VGS = 0 V,
f = 1.0 MHz
P-Channel
VDS = -10 V, VGS = 0 V,
f = 1.0 MHz
Type Min Typ Max Units
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
25
-25
P-Ch
N-Ch
P-Ch
V
25 mV /oC
-20
1 µA
10
-1 µA
-10
100 nA
-100 nA
N-Ch
-2.1
P-Ch
1.9
N-Ch 0.65 0.85
P-Ch -0.65 -1
N-Ch
3.8
6.3
3.1
P-Ch
10.6
15
7.9
N-Ch 0.2
P-Ch -0.05
N-Ch
0.2
P-Ch
0.135
mV / oC
1.5 V
-1.5
5
9
4
13
21
10
A
S
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
9.5
11
6
7
1.3
1.4
pF
pF
pF
www.onsemi.com
2


Features FDC6320C Dual N & P Channel , Digital FE T General Description These dual N & P Channel logic level enhancement mode f ield effect transistors are produced us ing ON Semiconductor's proprietary, hig h cell density, DMOS technology. This v ery high density process is especially tailored to minimize on-state resistanc e. The device is an improved design esp ecially for low voltage applications as a replacement for bipolar digital tran sistors in load switching applications. Since bias resistors are not required, this dual digital FET can replace seve ral digital transistors with difference bias resistors. Features N-Ch 25 V, 0 .22 A, RDS(ON) = 5 Ω @ VGS= 2.7 V. P- Ch 25 V, -0.12 A, RDS(ON) = 13 Ω @ VG S= -2.7 V. Very low level gate drive re quirements allowing direct operation in 3 V circuits. VGS(th) < 1.5 V. Gate-So urce Zener for ESD ruggedness. >6kV Hum an Body Model Replace NPN & PNP digital transistors. SOT-23 SuperSOTTM-6 Su perSOTTM-8 SO-8 SOT-223 SOIC-16 43 52 61 Absolute Maximum Ra.
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