CAT9554 I/O Port Datasheet

CAT9554 Datasheet, PDF, Equivalent


Part Number

CAT9554

Description

8-bit I2C and SMBus I/O Port

Manufacture

ON Semiconductor

Total Page 14 Pages
Datasheet
Download CAT9554 Datasheet


CAT9554
CAT9554, CAT9554A
8-bit I2C and SMBus I/O Port
with Interrupt
Description
The CAT9554 and CAT9554A are CMOS devices that provide 8bit
parallel input/output port expansion for I2C and SMBus compatible
applications. These I/O expanders provide a simple solution in
applications where additional I/Os are needed: sensors, power
switches, LEDs, pushbuttons, and fans.
The CAT9554/9554A consist of an input port register, an output port
register, a configuration register, a polarity inversion register and an
I2C/SMBuscompatible serial interface.
Any of the eight I/Os can be configured as an input or output by
writing to the configuration register. The system master can invert the
CAT9554/9554A input data by writing to the activehigh polarity
inversion register.
The CAT9554/9554A features an active low interrupt output which
indicates to the system master that an input state has changed.
The device’s extended addressing capability allows up to 8 devices
to share the same bus. The CAT9554A is identical to the CAT9554
except the fixed part of the I2C slave address is different. This allows
up to 16 of devices (eight CAT9554 and eight CAT9554A) to be
connected on the same bus.
Features
400 kHz I2C Bus Compatible (Note 1)
2.3 V to 5.5 V Operation
Low Standby Current
5 V Tolerant I/Os
8 I/O Pins that Default to Inputs at Powerup
High Drive Capability
Individual I/O Configuration
Polarity Inversion Register
Active Low Interrupt Output
Internal Poweron Reset
No Glitch on Powerup
Noise Filter on SDA/SCL Inputs
Cascadable up to 8 Devices
Industrial Temperature Range
16lead SOIC and TSSOP, and 16pad TQFN (4 x 4 mm) Packages
These Devices are PbFree, Halogen Free/BFR Free and are RoHS
Compliant
Applications
White Goods (dishwashers, washing machines)
Handheld Devices (cell phones, PDAs, digital cameras)
Data Communications (routers, hubs and servers)
1. All I/Os are set to inputs at RESET.
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SOIC16
W SUFFIX
CASE 751BG
TQFN16
HV4 SUFFIX
CASE 510AE
TSSOP16
Y SUFFIX
CASE 948AN
PIN CONNECTIONS
1
A0
A1
VCC
SDA
A2 SCL
I/O0 INT
I/O1 I/O7
I/O2 I/O6
I/O3 I/O5
VSS I/O4
SOIC (W), TSSOP (Y)
(Top View)
1
A2
I/O0
I/O1
I/O2
SCL
INT
I/O7
I/O6
TQFN 4 x 4 mm (HV4)
(Top View)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 14 of this data sheet.
© Semiconductor Components Industries, LLC, 2011
June, 2011 Rev. 6
1
Publication Order Number:
CAT9554/D

CAT9554
CAT9554, CAT9554A
A0
A1
A2
SCL
SDA
VCC
VSS
INPUT
FILTER
POWERON
RESET
I2C/SMBUS
CONTROL
8BIT
WRITE pulse
READ pulse
INPUT/
OUTPUT
PORTS
LP FILTER
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
VCC
I/O7
INT
Table 1. PIN DESCRIPTION
SOIC / TSSOP
1
2
3
47
8
912
13
14
15
16
TQFN
15
16
1
25
6
710
11
12
13
14
Figure 1. Block Diagram
Note: All I/Os are set to inputs at RESET.
Pin Name
A0
A1
A2
I/O03
VSS
I/O47
INT
SCL
SDA
VCC
Function
Address Input 0
Address Input 1
Address Input 2
Input/Output Port 0 to Input/Output Port 3
Ground
Input/Output Port 4 to Input/Output Port 7
Interrupt Output (open drain)
Serial Clock
Serial Data
Power Supply
Table 2. ABSOLUTE MAXIMUM RATINGS
Parameters
Ratings
Units
VCC with Respect to Ground
Voltage on Any Pin with Respect to Ground
0.5 to +6.5
0.5 to +5.5
V
V
DC Current on I/O0 to I/O7
DC Input Current
±50 mA
±20 mA
VCC Supply Current
VSS Supply Current
Package Power Dissipation Capability (TA = 25°C)
Junction Temperature
85
100
1.0
+150
mA
mA
W
°C
Storage Temperature
65 to +150
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Table 3. RELIABILITY CHARACTERISTICS
Symbol
Parameter
Reference Test Method
VZAP (Note 2)
ESD Susceptibility
JEDEC Standard JESD 22
ILTH (Notes 2, 3)
Latchup
JEDEC Standard 17
2. This parameter is tested initially and after a design or process change that affects the parameter.
3. Latchup protection is provided for stresses up to 100 mA on address and data pins from 1 V to VCC +1 V.
Min
2000
100
Units
Volts
mA
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2


Features CAT9554, CAT9554A 8-bit I2C and SMBus I /O Port with Interrupt Description The CAT9554 and CAT9554A are CMOS devices t hat provide 8−bit parallel input/outp ut port expansion for I2C and SMBus com patible applications. These I/O expande rs provide a simple solution in applica tions where additional I/Os are needed: sensors, power switches, LEDs, pushbut tons, and fans. The CAT9554/9554A consi st of an input port register, an output port register, a configuration registe r, a polarity inversion register and an I2C/SMBus−compatible serial interfac e. Any of the eight I/Os can be configu red as an input or output by writing to the configuration register. The system master can invert the CAT9554/9554A in put data by writing to the active−hig h polarity inversion register. The CAT9 554/9554A features an active low interr upt output which indicates to the syste m master that an input state has change d. The device’s extended addressing c apability allows up to 8 devices to share the same bus. The CAT9554A is.
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