PCA9517A I2C-Bus Repeater Datasheet

PCA9517A Datasheet, PDF, Equivalent


Part Number

PCA9517A

Description

Level-Translating I2C-Bus Repeater

Manufacture

ON Semiconductor

Total Page 14 Pages
Datasheet
Download PCA9517A Datasheet


PCA9517A
PCA9517A
Level-Translating I2C-Bus
Repeater
The PCA9517A is an I2C−bus repeater that provides level shifting
between low voltage (down to 0.9 V) and higher voltage (2.7 V to
5.5 V) for I2C−bus or SMBus applications.
Features
2 Channel, Bidirectional Buffer Isolates Capacitance and Allows
400 pF on Either Side of the Device
Voltage Level Translation from 0.9 V to 5.5 V and from 2.7 V to
5.5 V
Footprint and Functional Replacement for PCA9515/15A
I2C−bus and SMBus Compatible
Active HIGH Repeater Enable
Open−Drain Inputs/Outputs
Lock−up Free Operation
Supports Arbitration and Clock Stretching Across the Repeater, and
Multiple Masters
I2C and SMBus SCL Clock Frequency up to 1 MHz (The maximum
system operating frequency may be less than 1 MHz because of the
delays added by the repeater.)
Powered−Off High−Impedance I2C−bus Pins
A Side Operating Supply Voltage Range of 0.9 V to 5.5 V
B Side Operating Supply Voltage Range of 2.7 V to 5.5 V
5 V Tolerant I2C−bus and Enable Pins
Available in: Micro−8, SOIC8
ESD Performance: 8 kV HBM, 700 V MM, 2000 V CDM
These are Pb−Free Devices
www.onsemi.com
Micro8]
DM SUFFIX
CASE 846A
MARKING
DIAGRAMS
8
9517
AYWG
G
1
8
1
SOIC−8
CASE 751
8
9517
AYWW
G
1
A = Assembly Location
L = Wafer Lot
M = Date Code
Y = Year
W = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information on page 12 of
this data sheet.
© Semiconductor Components Industries, LLC, 2014
May, 2018 − Rev. 2
1
Publication Order Number:
PCA9517A/D

PCA9517A
PCA9517A
General Description
The PCA9517A is an I2C−bus repeater that provides level
shifting between low voltage (down to 0.9 V) and higher
voltage (2.7 V to 5.5 V) for I2C−bus or SMBus applications.
While retaining all the operating modes and features of the
I2C−bus system during the level shifts, it also permits
extension of the I2C−bus by providing bidirectional
buffering for both the data (SDA) and the clock (SCL) lines,
thus enabling two buses of 400 pF. Using the PCA9517A
enables the system designer to isolate two halves of a bus for
both voltage and capacitance. The SDA and SCL pins are
overvoltage tolerant and are high−impedance when the
PCA9517A is unpowered.
The 2.7 V to 5.5 V bus B side drivers behave much like the
drivers on the PCA9515A device, while the adjustable
voltage bus A side drivers drive more current and eliminate
the static offset voltage. This results in a LOW on the B side
translating into a nearly 0 V LOW on the A side which
accommodates smaller voltage swings of lower voltage
logic.
The static offset design of the B side PCA9517A I/O
drivers prevents them from being connected to another
device that has a rise time accelerator including the
PCA9510, PCA9511, PCA9512, PCA9513, PCA9514,
PCA9515A, PCA9516A, PCA9517A (port B), or
PCA9518. The A side of two or more PCA9517As can be
connected together, however, to allow a star topology with
the A side on the common bus, and the A side can be
connected directly to any other buffer with static or dynamic
offset voltage. Multiple PCA9517As can be connected in
series, A side to B side, with no build−up in offset voltage
with only time−of−flight delays to consider.
The PCA9517A drivers are not enabled unless the bus is
idle, VCC(A) is above 0.8 V and VCC(B) is above 2.5 V. The
EN pin can also be used to turn the drivers on and off under
system control. Caution should be observed to only change
the state of the enable pin when the bus is idle.
The output pull−down on the B side internal buffer LOW
is set for approximately 0.5 V, while the input threshold of
the internal buffer is set about 70 mV lower (0.43 V). When
the B side I/O is driven LOW internally, the LOW is not
recognized as a LOW by the input. This prevents a lock−up
condition from occurring. The output pull−down on the A
side drives a hard LOW and the input level is set at
0.3 VCC(A) to accommodate the need for a lower LOW level
in systems where the low voltage side supply voltage is as
low as 0.9 V.
BLOCK DIAGRAM
Figure 1. Block Diagram of PCA9517A
www.onsemi.com
2


Features PCA9517A Level-Translating I2C-Bus Repe ater The PCA9517A is an I2C−bus repea ter that provides level shifting betwee n low voltage (down to 0.9 V) and highe r voltage (2.7 V to 5.5 V) for I2C−bu s or SMBus applications. Features • 2 Channel, Bidirectional Buffer Isolates Capacitance and Allows 400 pF on Eithe r Side of the Device • Voltage Level Translation from 0.9 V to 5.5 V and fro m 2.7 V to 5.5 V • Footprint and Func tional Replacement for PCA9515/15A • I2C−bus and SMBus Compatible • Acti ve HIGH Repeater Enable • Open−Drai n Inputs/Outputs • Lock−up Free Ope ration • Supports Arbitration and Clo ck Stretching Across the Repeater, and Multiple Masters • I2C and SMBus SCL Clock Frequency up to 1 MHz (The maximu m system operating frequency may be les s than 1 MHz because of the delays adde d by the repeater.) • Powered−Off H igh−Impedance I2C−bus Pins • A Si de Operating Supply Voltage Range of 0. 9 V to 5.5 V • B Side Operating Supply Voltage Range of 2.7 V to 5.5 V • 5 V Tolerant I2C−bus and Ena.
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