CM2006 EMI Filter Datasheet

CM2006 Datasheet, PDF, Equivalent


Part Number

CM2006

Description

LCD and Camera EMI Filter

Manufacture

ON Semiconductor

Total Page 6 Pages
Datasheet
Download CM2006 Datasheet


CM2006
CM2006
Praetorian) L-C LCD and
Camera EMI Filter Array
with ESD Protection
Product Description
The CM2006 connects between the VGA or DVI−I port connector
and the internal analog or digital flat panel controller logic. The
CM2006 incorporates ESD protection for all signals, level shifting for
the DDC signals and buffering for the SYNC signals. ESD protection
for the video, DDC and SYNC lines is implemented with
low−capacitance current steering diodes.
All connector interface pins are designed to safely handle the high
current spikes specified by IEC−61000−4−2 Level 4 (±8 kV contact
discharge). The ESD protection for the DDC, SYNC and VIDEO
signal pins is designed to prevent “backdrive current” when the device
is powered down while connected to a video source that is powered up.
Separate positive supply rails are provided for the VIDEO / SYNC
signals and DDC signals to facilitate interfacing with low voltage
video controller ICs and microcontrollers to provide design flexibility
in multi−supply−voltage environments.
Two Schmitt−triggered non−inverting buffers redrive and condition
the HSYNC and VSYNC signals from the video connector (SYNC1,
SYNC2). These buffers accept VESA VSIS compliant TTL input
signals and convert them to CMOS output levels that swing between
ground and VCC.
Two N−channel MOSFETs provide the level shifting function
required when the DDC controller or EDID EEPROM is operated at a
lower supply voltage than the monitor. The gate terminals for these
MOSFETS (VCC_DDC) should be connected to the supply rail
(typically 3.3 V, 2.5 V, etc.) that supplies power to the transceivers of
the DDC controller.
www.onsemi.com
QSOP16
QR SUFFIX
CASE 492
MARKING DIAGRAM
CMDYYWW
CM2006
02QR
CM2006−02QR = Specific Device Code
YY = Year
WW = Work Week
ORDERING INFORMATION
Device
Package
Shipping
CM2006−02QR
QSOP−16 2500/Tape & Reel
(Pb−Free)
Features
Includes ESD Protection, Level−Shifting, Buffering and Sync
Impedance Matching
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
VESA VSIS Version 1 Revision 2 Compatible Interface
Supports Optional NAVI Signalling Requirements
7 Channels of ESD Protection for all VGA Port
Bidirectional Level Shifting N−Channel FETs Provided
Connector Pins. All Pins Meet IEC−61000−4−2 Level 4
for DDC_CLK & DDC_DATA Channels
ESD Requirements (±8 kV Contact Discharge)
Very Low Loading Capacitance from ESD Protection
Diodes on VIDEO Lines (3 pF Maximum)
Backdrive Protection on all Lines
Compact 16−Lead QSOP Package
Schmitt−Triggered Input Buffers for HSYNC and
VSYNC Lines
These Devices are Pb−Free and are RoHS Compliant
Applications
VGA and DVI−I Ports in:
Monitors
TVs
© Semiconductor Components Industries, LLC, 2016
January, 2016 − Rev. 4
1
Publication Order Number:
CM2006/D

CM2006
CM2006
ELECTRICAL SCHEMATIC
VCC_DDC
BYP
8
7
VCC
1
10
DDC_OUT1
11 DDC_OUT2
VIDEO_1
VIDEO_2
VIDEO_3
3
4
5
6
GND
DDC_IN1
DDC_IN2
ENABLE
SYNC_IN1
SYNC_IN2
9
12
2
13
15
GND
RT RT
16 SYNC_OUT2
14 SYNC_OUT1
PACKAGE / PINOUT DIAGRAM
Top View
VCC
ENABLE
VIDEO_1
VIDEO_2
VIDEO_3
GND
VCC_DDC
BYP
1 16
2 15
3 14
4 13
5 12
6 11
7 10
89
16 Pin QSOP
SYNC_OUT2
SYNC_IN2
SYNC_OUT1
SYNC_IN1
DDC_IN2
DDC_OUT2
DDC_OUT1
DDC_IN1
Table 1. PIN DESCRIPTIONS
Lead(s)
Name
Description
1 VCC This is a supply input for the SYNC_1 and SYNC_2 level shifters, video protection and the DDC circuits.
2
ENABLE
Active high enable. Disables the Sync buffer outputs when low.
3
VIDEO_1
Video signal ESD protection channel. This pin is typically tied one of the video lines between the control-
ler device and the video connector.
4
VIDEO_2
Video signal ESD protection channel. This pin is typically tied one of the video lines between the control-
ler device and the video connector.
5
VIDEO_3
Video signal ESD protection channel. This pin is typically tied one of the video lines between the control-
ler device and the video connector.
6
GND
Ground reference supply pin.
7
VCC_DDC
This is an isolated supply input for the DDC_1 and DDC_2 level−shifting N−FET gates.
8
BYP
An external 0.22 mF bypass capacitor is required on this pin.
9
DDC_IN1
DDC signal input. Connects to the video connector side of one of the DDC lines.signal output.
10 DDC_OUT1 DDC signal output. Connects to the monitor DDC logic.
11
DDC_OUT
DDC signal output. Connects to the monitor DDC logic.
12
DDC_IN2
DDC signal input. Connects to the video connector side of one of the DDC lines
13
SYNC_IN1
Sync signal buffer input. Connects to the video connector side of one of the sync lines.
14 SYNC_OUT1 Sync signal buffer output. Connects to the monitor SYNC logic.
15
SYNC_IN2
Sync signal buffer input. Connects to the video connector side of one of the sync lines.
16 SYNC_OUT2 Sync signal buffer output. Connects to the monitor SYNC logic.
www.onsemi.com
2


Features CM2006 Praetorian) L-C LCD and Camera E MI Filter Array with ESD Protection Pr oduct Description The CM2006 connects b etween the VGA or DVI−I port connecto r and the internal analog or digital fl at panel controller logic. The CM2006 i ncorporates ESD protection for all sign als, level shifting for the DDC signals and buffering for the SYNC signals. ES D protection for the video, DDC and SYN C lines is implemented with low−capac itance current steering diodes. All con nector interface pins are designed to s afely handle the high current spikes sp ecified by IEC−61000−4−2 Level 4 (±8 kV contact discharge). The ESD pro tection for the DDC, SYNC and VIDEO sig nal pins is designed to prevent “back drive current” when the device is pow ered down while connected to a video so urce that is powered up. Separate posit ive supply rails are provided for the V IDEO / SYNC signals and DDC signals to facilitate interfacing with low voltage video controller ICs and microcontrollers to provide design flexibility in mu.
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