FDG6322C Digital FET Datasheet

FDG6322C Datasheet, PDF, Equivalent


Part Number

FDG6322C

Description

Dual N & P Channel Digital FET

Manufacture

ON Semiconductor

Total Page 9 Pages
Datasheet
Download FDG6322C Datasheet


FDG6322C
FDG6322C
Dual N & P Channel Digital FET
General Description
These dual N & P-Channel logic level enhancement mode
field effect transistors are produced using ON
Semiconductor's proprietary, high cell density, DMOS
technology. This very high density process is especially
tailored to minimizeon-state resistance. This device
has been designed especially for low voltage applications
as a replacement for bipolar digital transistors and small
signal MOSFETs. Since bias resistors are not required,
this dual digital FET can replace several different digital
transistors, with different bias resistor values.
Features
N-Ch 0.22 A, 25 V, RDS(ON) = 4.0 @ VGS= 4.5 V,
RDS(ON) = 5.0 @ VGS= 2.7 V.
P-Ch -0.41 A,-25V, RDS(ON) = 1.1 @ VGS= -4.5V,
RDS(ON) = 1.5 @ VGS= -2.7V.
Very small package outline SC70-6.
Very low level gate drive requirements allowing direct
operation in 3 V circuits (VGS(th) < 1.5 V).
Gate-Source Zener for ESD ruggedness
(>6kV Human Body Model).
SC70-6
SOT-23
SuperSOTTM-6
SOT-8
SO-8
SOIC-14
S2
G2
D1
pin 1
SC70-6
Mark: .22
D2
G1
S1
16
Q1
25
Q2
34
Absolute Maximum Ratings TA = 25oC unless other wise noted
Symbol Parameter
N-Channel
VDSS Drain-Source Voltage
VGSS Gate-Source Voltage
ID Drain Current - Continuous
- Pulsed
25
8
0.22
0.65
PD
TJ,TSTG
ESD
Maximum Power Dissipation
(Note 1)
Operating and Storage Temperature Range
Electrostatic Discharge Rating MIL-STD-883D
Human Body Model (100pf / 1500 Ohm)
THERMAL CHARACTERISTICS
RθJA Thermal Resistance, Junction-to-Ambient (Note1)
0.3
-55 to 150
6
415
P-Channel
-25
-8
-0.41
-1.2
Units
V
V
A
W
°C
kV
°C/W
© 2012 Semiconductor Components Industries, LLC.
October-2017, Rev. 6
Publication Order Number:
FDG6322C/D

FDG6322C
DMOS Electrical Characteristics (TA = 25 OC unless otherwise noted )
Symbol
Parameter
Conditions
OFF CHARACTERISTICS
BVDSS
Drain-Source Breakdown Voltage
BVDSS/TJ Breakdown Voltage Temp. Coefficient
IDSS Zero Gate Voltage Drain Current
IDSS Zero Gate Voltage Drain Current
IGSS Gate - Body Leakage Current
ON CHARACTERISTICS (Note 2)
VGS(th)
Gate Threshold Voltage
VGS(th)/TJ Gate Threshold Voltage Temp. Coefficient
RDS(ON)
Static Drain-Source On-Resistance
ID(ON) On-State Drain Current
gFS Forward Transconductance
DYNAMIC CHARACTERISTICS
Ciss Input Capacitance
Coss Output Capacitance
Crss Reverse Transfer Capacitance
VGS = 0 V, ID = 250 µA
VGS = 0 V, ID = -250 µA
ID = 250 µA, Referenced to 25 oC
ID = -250 µA, Referenced to 25 oC
VDS = 20 V, VGS= 0 V,
TJ = 55°C
VDS =-20 V, VGS = 0 V,
TJ = 55°C
VGS = 8 V, VDS = 0 V
VGS = -8 V, VDS = 0 V
VDS = VGS, ID = 250 µA
VDS = VGS, ID = -250 µA
ID = 250 µA, Referenced to 25 o C
ID= -250 µA, Referenced to 25 o C
VGS = 4.5 V, ID = 0.22 A
TJ =125°C
VGS = 2.7 V, ID = 0.19 A
VGS = -4.5 V, ID = -0.41 A
TJ =125°C
VGS = -2.7 V, ID = -0.25 A
VGS = 4.5 V, VDS = 5 V
VGS = -4.5 V, VDS = -5 V
VDS = 5 V, ID= 0.22 A
VDS = -5 V, ID = -0.5 A
N-Channel
VDS = 10 V, VGS= 0 V,
f = 1.0 MHz
P-Channel
VDS = -10 V, VGS = 0 V,
f = 1.0 MHz
Type Min Typ
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
25
-25
25
-22
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
0.65
-0.65
0.22
-0.41
0.85
-0.82
-2.1
2.1
2.6
5.3
3.7
0.85
1.2
1.15
0.2
0.9
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
9.5
62
6
34
1.3
10
Max Units
V
mV/oC
1 µA
10
-1 µA
-10
100 nA
-100 nA
1.5 V
-1.5
mV/ oC
4
7
5
1.1
1.9
1.5
A
S
pF
www.onsemi.com
2


Features FDG6322C Dual N & P Channel Digital FET General Description These dual N & P-Ch annel logic level enhancement mode fiel d effect transistors are produced using ON Semiconductor's proprietary, high c ell density, DMOS technology. This very high density process is especially tai lored to minimizeon-state resistance. T his device has been designed especially for low voltage applications as a repl acement for bipolar digital transistors and small signal MOSFETs. Since bias r esistors are not required, this dual di gital FET can replace several different digital transistors, with different bi as resistor values. Features N-Ch 0.22 A, 25 V, RDS(ON) = 4.0 Ω @ VGS= 4.5 V, RDS(ON) = 5.0 Ω @ VGS= 2.7 V. P-Ch -0.41 A,-25V, RDS(ON) = 1.1 Ω @ VGS= -4.5V, RDS(ON) = 1.5 Ω @ VGS= -2.7V. Very small package outline SC70-6. Ver y low level gate drive requirements all owing direct operation in 3 V circuits (VGS(th) < 1.5 V). Gate-Source Zener fo r ESD ruggedness (>6kV Human Body Model). SC70-6 SOT-23 SuperSOTTM-6.
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