FDG6322C Dual N & P Channel Digital FET
General Description
These dual N & P-Channel logic level enhancement mode field ...
FDG6322C Dual N & P Channel Digital FET
General Description
These dual N & P-Channel logic level enhancement mode field effect
transistors are produced using ON Semiconductor's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimizeon-state resistance. This device has been designed especially for low voltage applications as a replacement for bipolar digital
transistors and small signal MOSFETs. Since bias resistors are not required, this dual digital FET can replace several different digital
transistors, with different bias resistor values.
Features
N-Ch 0.22 A, 25 V, RDS(ON) = 4.0 Ω @ VGS= 4.5 V, RDS(ON) = 5.0 Ω @ VGS= 2.7 V.
P-Ch -0.41 A,-25V, RDS(ON) = 1.1 Ω @ VGS= -4.5V, RDS(ON) = 1.5 Ω @ VGS= -2.7V.
Very small package outline SC70-6.
Very low level gate drive requirements allowing direct operation in 3 V circuits (VGS(th) < 1.5 V).
Gate-Source Zener for ESD ruggedness (>6kV Human Body Model).
SC70-6
SOT-23
SuperSOTTM-6
SOT-8
SO-8
SOIC-14
S2 G2 D1
pin 1
SC70-6 Mark: .22
D2 G1 S1
16
Q1
25
Q2
34
Absolute Maximum Ratings TA = 25oC unless other wise noted
Symbol Parameter
N-Channel
VDSS Drain-Source Voltage VGSS Gate-Source Voltage ID Drain Current - Continuous
- Pulsed
25 8 0.22 0.65
PD TJ,TSTG ESD
Maximum Power Dissipation
(Note 1)
Operating and Storage Temperature Range
Electrostatic Discharge Rating MIL-STD-883D Human Body Model (100pf / 1500 Ohm)
THERMAL CHARACTERISTICS
RθJA Thermal Resista...