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STM32L4S5xx STM32L4S7xx STM32L4S9xx
Ultra-low-power Arm® Cortex®-M4 32-bit MCU+FPU, 150DMIPS, up to 2MB Flash, 640KB SRAM, LCD-TFT & MIPI DSI, AES+HASH
Datasheet- production data
Features
• Ultra-low-power with FlexPowerControl – 1.71 V to 3.6 V power supply – -40 °C to 85/125 °C temperature range – Batch acquisition mode (BAM) – 305 nA in VBAT mode: supply for RTC and 32x32-bit backup registers – 33 nA Shutdown mode (5 wakeup pins) – 125 nA Standby mode (5 wakeup pins) – 420 nA Standby mode with RTC – 2.8 μA Stop 2 with RTC – 110 μA/MHz Run mode – 5 µs wakeup from Stop mode – Brownout reset (BOR) in all modes except Shutdown – Interconnect matrix
• Core: Arm® 32-bit Cortex®-M4 CPU with FPU, adaptive real-time accelerator (ART Accelerator) allowing 0-wait-state execution from Flash memory, frequency up to 120 MHz, MPU, 150 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions
• Performance benchmark – 1.25 DMIPS/MHz (Drystone 2.1) – 409.20 CoreMark® (3.41 CoreMark/MHz @120 MHz)
• Energy benchmark – 233 ULPMark™CP score – 56.5 ULPMark™PP score
• Clock sources – 4 to 48 MHz crystal oscillator – 32 kHz crystal oscillator for RTC (LSE) – Internal 16 MHz factory-trimmed RC (±1%) – Internal low-power 32 kHz RC (±5%) – Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by LSE (better than ±0.25 % accuracy) – Internal 48 MHz with clock recovery
LQFP144 (20 × 20) UFBGA169 (7 x 7) LQFP100 (14 x 14) UFBGA144 (10 x 10)
UFBGA132 (7 × 7)
WLCSP144 (pitch 0.4 mm)
– 3 PLLs for system clock, USB, audio, ADC
• RTC with hardware calendar, alarms and calibration
• Up to 24 capacitive sensing channels: support touchkey, linear and rotary touch sensors
• Advanced graphics features – Chrom-ART Accelerator (DMA2D) for enhanced graphic content creation
– Chrom-GRC (GFXMMU) allowing up to 20% of graphic resources optimization
– MIPI® DSI Host controller with two DSI lanes running at up to 500 Mbit/s each
– LCD-TFT controller
• 16x timers: 2 x 16-bit advanced motor-control, 2 x 32-bit and 5 x 16-bit general purpose, 2x 16-bit basic, 2x low-power 16-bit timers (available in Stop mode), 2x watchdogs, SysTick timer
• Up to 136 fast I/Os, most 5 V-tolerant, up to 14 I/Os with independent supply down to 1.08 V
• Memories – 2-Mbyte Flash, 2 banks read-while-write, proprietary code readout protection
– 640 Kbytes of SRAM including 64 Kbytes with hardware parity check
– External memory interface for static memories supporting SRAM, PSRAM, NOR, NAND and FRAM memories
– 2 x Octo-SPI memory interface
• 4x digital filters for sigma delta modulator
• Rich analog peripherals (independent supply) – 12-bit ADC 5 Msps, up to 16-bit with hardware oversampling, 200 µA/Msps
March 2020
This is information on a product in full production.
DS12024 Rev 4
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STM32L4S5xx, STM32L4S7xx and STM32L4S9xx
– 2x 12-bit DAC, low-power sample and hold – 2x operational amplifiers with built-in PGA – 2x ultra-low-power comparators
• 20x communication interfaces – USB OTG 2.0 full-speed, LPM and BCD – 2x SAIs (serial audio interface) – 4x I2C FM+(1 Mbit/s), SMBus/PMBus – 6x USARTs (ISO 7816, LIN, IrDA, modem) – 3x SPIs (5x SPIs with the dual Octo-SPI) – CAN (2.0B Active) and SDMMC
• 14-channel DMA controller
• True random number generator
• CRC calculation unit, 96-bit unique ID
• 8- to 14-bit camera interface up to 32 MHz (black and white) or 10 MHz (color)
• Encryption hardware accelerator: AES (128/256-bit key), HASH (SHA-256)
• Development support: serial wire debug
(SWD), JTAG, Embedded Trace Macrocell™
(ETM)
Reference STM32L4S5xx STM32L4S7xx STM32L4S9xx
Table 1. Device summary Part numbers
STM32L4S5VI, STM32L4S5QI, STM32L4S5ZI, STM32L4S5AI STM32L4S7VI, STM32L4S7ZI, STM32L4S7AI STM32L4S9VI, STM32L4S9ZI, STM32L4S9AI
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DS12024 Rev 4
STM32L4S5xx, STM32L4S7xx and STM32L4S9xx
Contents
Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3
Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.1 Arm® Cortex®-M4 core with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.2 Adaptive real-time memory accelerator (ART Accelerator) . . . . . . . . . . . 17
3.3 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.4 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.5 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.6 Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.7 Firewall . . . . . . . . . . . . . . . . . . . . .