DDR3L SDRAM. W634GU6NB Datasheet


W634GU6NB SDRAM. Datasheet pdf. Equivalent


Part Number

W634GU6NB

Description

32M x 8-BANKS x 16-BIT DDR3L SDRAM

Manufacture

Winbond

Total Page 30 Pages
Datasheet
Download W634GU6NB Datasheet


W634GU6NB
W634GU6NB
32M 8 BANKS 16 BIT DDR3L SDRAM
Table of Contents-
1. GENERAL DESCRIPTION ...................................................................................................................5
2. FEATURES ...........................................................................................................................................5
3. ORDER INFORMATION .......................................................................................................................6
4. KEY PARAMETERS .............................................................................................................................7
5. BALL CONFIGURATION ......................................................................................................................9
6. BALL DESCRIPTION..........................................................................................................................10
7. BLOCK DIAGRAM ..............................................................................................................................12
8. FUNCTIONAL DESCRIPTION............................................................................................................13
8.1 Basic Functionality ..............................................................................................................................13
8.2 RESET and Initialization Procedure ....................................................................................................13
8.2.1
Power-up Initialization Sequence .....................................................................................13
8.2.2
Reset Initialization with Stable Power ..............................................................................15
8.3 Programming the Mode Registers.......................................................................................................16
8.3.1
Mode Register MR0 .........................................................................................................18
8.3.1.1
Burst Length, Type and Order ................................................................................19
8.3.1.2
CAS Latency...........................................................................................................19
8.3.1.3
Test Mode...............................................................................................................20
8.3.1.4
DLL Reset...............................................................................................................20
8.3.1.5
Write Recovery .......................................................................................................20
8.3.1.6
Precharge PD DLL .................................................................................................20
8.3.2
Mode Register MR1 .........................................................................................................21
8.3.2.1
DLL Enable/Disable................................................................................................21
8.3.2.2
Output Driver Impedance Control ...........................................................................22
8.3.2.3
ODT RTT Values ....................................................................................................22
8.3.2.4
Additive Latency (AL) .............................................................................................22
8.3.2.5
Write leveling ..........................................................................................................22
8.3.2.6
Output Disable........................................................................................................22
8.3.3
Mode Register MR2 .........................................................................................................23
8.3.3.1
Partial Array Self Refresh (PASR) ..........................................................................24
8.3.3.2
CAS Write Latency (CWL) ......................................................................................24
8.3.3.3
Auto Self Refresh (ASR) and Self Refresh Temperature (SRT) .............................24
8.3.3.4
Dynamic ODT (Rtt_WR) .........................................................................................24
8.3.4
Mode Register MR3 .........................................................................................................25
8.3.4.1
Multi Purpose Register (MPR) ................................................................................25
8.4 No OPeration (NOP) Command..........................................................................................................26
8.5 Deselect Command.............................................................................................................................26
8.6 DLL-off Mode ......................................................................................................................................26
8.7 DLL on/off switching procedure...........................................................................................................27
8.7.1
DLL “on” to DLL “off” Procedure.......................................................................................27
8.7.2
DLL “off” to DLL “on” Procedure.......................................................................................28
8.8 Input clock frequency change .............................................................................................................29
8.8.1
Frequency change during Self-Refresh............................................................................29
8.8.2
Frequency change during Precharge Power-down ..........................................................29
8.9 Write Leveling .....................................................................................................................................31
8.9.1
DRAM setting for write leveling & DRAM termination function in that mode ....................32
Publication Release Date: Jul. 29, 2019
Revision: A01
-1-

W634GU6NB
W634GU6NB
8.9.2
Write Leveling Procedure.................................................................................................32
8.9.3
Write Leveling Mode Exit .................................................................................................34
8.10 Multi Purpose Register........................................................................................................................35
8.10.1
MPR Functional Description.............................................................................................36
8.10.2
MPR Register Address Definition.....................................................................................37
8.10.3
Relevant Timing Parameters............................................................................................37
8.10.4
Protocol Example .............................................................................................................37
8.11 ACTIVE Command..............................................................................................................................43
8.12 PRECHARGE Command....................................................................................................................43
8.13 READ Operation .................................................................................................................................44
8.13.1
READ Burst Operation .....................................................................................................44
8.13.2
READ Timing Definitions..................................................................................................45
8.13.2.1
READ Timing; Clock to Data Strobe relationship....................................................46
8.13.2.2
READ Timing; Data Strobe to Data relationship .....................................................47
8.13.2.3
tLZ(DQS), tLZ(DQ), tHZ(DQS), tHZ(DQ) Calculation .............................................48
8.13.2.4
tRPRE Calculation..................................................................................................49
8.13.2.5
tRPST Calculation ..................................................................................................49
8.13.2.6
Burst Read Operation followed by a Precharge......................................................55
8.14 WRITE Operation................................................................................................................................57
8.14.1
DDR3L Burst Operation ...................................................................................................57
8.14.2
WRITE Timing Violations .................................................................................................57
8.14.2.1
Motivation ...............................................................................................................57
8.14.2.2
Data Setup and Hold Violations..............................................................................57
8.14.2.3
Strobe to Strobe and Strobe to Clock Violations.....................................................57
8.14.2.4
Write Timing Parameters ........................................................................................57
8.14.3
Write Data Mask...............................................................................................................58
8.14.4
tWPRE Calculation...........................................................................................................59
8.14.5
tWPST Calculation ...........................................................................................................59
8.15 Refresh Command ..............................................................................................................................66
8.16 Self-Refresh Operation .......................................................................................................................68
8.17 Power-Down Modes............................................................................................................................70
8.17.1
Power-Down Entry and Exit .............................................................................................70
8.17.2
Power-Down clarifications - Case 1 .................................................................................76
8.17.3
Power-Down clarifications - Case 2 .................................................................................76
8.17.4
Power-Down clarifications - Case 3 .................................................................................77
8.18 ZQ Calibration Commands..................................................................................................................78
8.18.1
ZQ Calibration Description ...............................................................................................78
8.18.2
ZQ Calibration Timing ......................................................................................................79
8.18.3
ZQ External Resistor Value, Tolerance, and Capacitive loading......................................79
8.19 On-Die Termination (ODT) ..................................................................................................................80
8.19.1
ODT Mode Register and ODT Truth Table ......................................................................80
8.19.2
Synchronous ODT Mode..................................................................................................81
8.19.2.1
ODT Latency and Posted ODT...............................................................................81
8.19.2.2
Timing Parameters .................................................................................................81
8.19.2.3
ODT during Reads..................................................................................................83
8.19.3
Dynamic ODT ..................................................................................................................84
8.19.3.1
Functional Description: ...........................................................................................84
8.19.3.2
ODT Timing Diagrams............................................................................................85
8.19.4
Asynchronous ODT Mode................................................................................................89
Publication Release Date: Jul. 29, 2019
Revision: A01
-2-


Features W634GU6NB 32M  8 BANKS  16 BIT DD R3L SDRAM Table of Contents- 1. GENER AL DESCRIPTION ........................ ....................................... ....................................... .............5 2. FEATURES ........... ....................................... ....................................... ....................................... ...........5 3. ORDER INFORMATION .... ....................................... ....................................... .....................................6 4. KEY PARAMETERS .................... ....................................... ....................................... ...........................7 5. BALL C ONFIGURATION .......................... ....................................... ....................................... ..............9 6. BALL DESCRIPTION... ....................................... ....................................... ....................................... ..10 7. BLOCK DIAGRAM .............................................
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