SN74LS192 UP/DOWN COUNTER Datasheet

SN74LS192 Datasheet, PDF, Equivalent


Part Number

SN74LS192

Description

PRESETTABLE BCD/DECADE UP/DOWN COUNTER PRESETTABLE 4-BIT BINARY UP/DOWN COUNTER

Manufacture

ON Semiconductor

Total Page 7 Pages
Datasheet
Download SN74LS192 Datasheet


SN74LS192
SN74LS192
PRESETTABLE BCD/DECADE
UP/DOWN COUNTER
PRESETTABLE 4-BIT
BINARY UP/DOWN
COUNTER
http://onsemi.com
The SN54/74LS192 is an UP/DOWN BCD Decade (8421) Counter
and the SN54/74LS193 is an UP/DOWN MODULO-16 Binary
Counter. Separate Count Up and Count Down Clocks are used and in
either counting mode the circuits operate synchronously. The outputs
change state synchronous with the LOW-to-HIGH transitions on the
clock inputs.
Separate Terminal Count Up and Terminal Count Down outputs are
provided which are used as the clocks for a subsequent stages without
extra logic, thus simplifying multistage counter designs. Individual
preset inputs allow the circuits to be used as programmable counters.
Both the Parallel Load (PL) and the Master Reset (MR) inputs
asynchronously override the clocks.
Low Power . . . 95 mW Typical Dissipation
High Speed . . . 40 MHz Typical Count Frequency
Synchronous Counting
Asynchronous Master Reset and Parallel Load
Individual Preset Inputs
Cascading Circuitry Internally Provided
PRESETTABLE BCD/DECADE
UP/DOWN COUNTER
PRESETTABLE 4-BIT BINARY
UP/DOWN COUNTER
LOW POWER SCHOTTKY
16
1
16
1
J SUFFIX
CERAMIC
CASE 620-09
N SUFFIX
PLASTIC
CASE 648-08
CONNECTION DIAGRAM DIP (TOP VIEW)
VCC P0 MR TCD TCU PL P2 P3
16 15 14 13 12 11 10 9
NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as the Dual
In-Line Package.
1 2 3 4 56 78
P1 Q1 Q0 CPD CPU Q2 Q3 GND
PIN NAMES
LOADING (Note a)
HIGH
LOW
16
1
D SUFFIX
SOIC
CASE 751B-03
ORDERING INFORMATION
SN54LSXXXJ
SN74LSXXXN
SN74LSXXXD
Ceramic
Plastic
SOIC
LOGIC SYMBOL
11 15 1 10 9
CPU
CPD
MR
Count Up Clock Pulse Input
Count Down Clock Pulse Input
Asynchronous Master Reset (Clear) Input
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
PL Asynchronous Parallel Load (Active LOW) Input 0.5 U.L. 0.25 U.L.
Pn Parallel Data Inputs
0.5 U.L. 0.25 U.L.
Qn Flip-Flop Outputs (Note b)
10 U.L. 5 (2.5) U.L.
TCD Terminal Count Down (Borrow) Output (Note b) 10 U.L. 5 (2.5) U.L.
TCU Terminal Count Up (Carry) Output (Note b)
10 U.L. 5 (2.5) U.L.
NOTES:
a. 1 TTL Unit Load (U.L.) = 40 μA HIGH/1.6 mA LOW.
b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)
b. Temperature Ranges.
5
4
PL P0 P1 P2 P3
CPU TCU
CPD
MR Q0
Q1
Q2
Q3 TCD
14 3 2 6
VCC = PIN 16
GND = PIN 8
7
12
13
© Semiconductor Components Industries, LLC, 2006
July, 2006 Rev. 7
1
Publication Order Number:
SN74LS192/D

SN74LS192
STATE DIAGRAMS
0123
15
14
13
12 11 10
9
LS192
4
5
6
7
8
SN74LS192
Figure 2. LS192 LOGIC
EQUATIONS
FOR TERMINAL COUNT
Figure 1.
Figure 3.
TCU = Q0 Q3 CPU
TCD = Q0 Q1 Q2 Q3 CPD
Figure 4. LS193 LOGIC
EQUATIONS
FOR TERMINAL COUNT
Figure 5.
TCU = Q0 Q1Q2Q3 CPU
TCD = Q0 Q1 Q2 Q3 CPD
Count Up
Count Down
LOGIC DIAGRAMS
PL 11
(LOAD)
CPU 5
(UP COUNT)
P0
15
P1
1
P2
10
SD Q
T
CD Q
SD Q
T
CD Q
SD Q
T
CD Q
0123
15
14
13
12 11 10 9
LS193
4
5
6
7
8
P3
9
12 TCU
(CARRY
OUTPUT)
SD Q
T
CD Q
CPD 4
(DOWN
COUNT)
MR
14
(CLEAR)
VGCNCD==PPININ186
= PIN NUMBERS
3
Q0
2
Q1
LS192
6
Q2
13 TCD
(BORROW
OUTPUT)
7
Q3
http://onsemi.com
2


Features SN74LS192 PRESETTABLE BCD/DECADE UP/DOW N COUNTER PRESETTABLE 4-BIT BINARY UP/D OWN COUNTER http://onsemi.com The SN5 4/74LS192 is an UP/DOWN BCD Decade (842 1) Counter and the SN54/74LS193 is an U P/DOWN MODULO-16 Binary Counter. Separa te Count Up and Count Down Clocks are u sed and in either counting mode the cir cuits operate synchronously. The output s change state synchronous with the LOW -to-HIGH transitions on the clock input s. Separate Terminal Count Up and Termi nal Count Down outputs are provided whi ch are used as the clocks for a subsequ ent stages without extra logic, thus si mplifying multistage counter designs. I ndividual preset inputs allow the circu its to be used as programmable counters . Both the Parallel Load (PL) and the M aster Reset (MR) inputs asynchronously override the clocks. • Low Power . . . 95 mW Typical Dissipation • High Sp eed . . . 40 MHz Typical Count Frequenc y • Synchronous Counting • Asynchro nous Master Reset and Parallel Load • Individual Preset Inputs • Cascad.
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