DS110DF1610 16-Channel Retimer Datasheet

DS110DF1610 Datasheet, PDF, Equivalent


Part Number

DS110DF1610

Description

8.5- to 11.3-Gbps 16-Channel Retimer

Manufacture

etcTI

Total Page 30 Pages
Datasheet
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DS110DF1610
SNLS472A – JANUARY 2014 – REVISED JUNE 2017
DS110DF1610 8.5- to 11.3-Gbps 16-Channel Retimer
1 Features
1 Pin-Compatible Family
– DS150DF1610: 12.5 - 15G
– DS125DF1610: 9.8 to 12.5G
– DS110DF1610: 8.5 – 11.3G
• 4x4 Analog Cross Point Switch for Each Quad
• Fully-Adaptive CTLE
• Self-Tuning DFE, With Optional Continuous
Adaption
• On-Chip, AC-coupling on Receive Inputs
• Adjustable Transmit VOD
• Adjustable 3-Tap Transmit FIR Filter
• Locks to Half/Quarter/Eighth Data Rates For
Legacy Support
• On-Chip Eye Monitor (EOM), PRBS Checker,
PRBS Pattern Generator
• Supports IEEE 1149.1 and 1149.6
• Programmable Output Polarity Inversion
• Input Signal Detection, CDR Lock Detection
• Single 2.5-V ±5% Power Supply
• SMBus-Based Register Configuration
• Optional EEPROM Configuration
• 15-mm × 15-mm, 196-Pin FCBGA Package
• Operating Temp Range : –10°C to +85°C
Typical Application Diagram
2 Description
The DS110DF1610 is a sixteen-channel multi-rate
retimer with integrated signal conditioning. The device
includes a full adaptive Continuous Time Linear
Equalizer (CTLE), Decision Feedback Equalizer
(DFE), clock and data recovery (CDR), and a transmit
FIR filter to enhance the reach and robustness over
long, lossy, crosstalk impaired high speed serial links
to achieve BER < 1×10-15.
Each channel of the DS110DF1610 independently
locks to serial data at 8.5 to 11.3 Gbps and any
supported sub-multiple. A simple external oscillator
(±100ppm) that is synchronous or asynchronous with
the incoming data stream can be used as a reference
clock to speed up the lock process. Integrated 4x4
cross point switches allow for full non-blocking routing
or broadcasting within each quad of the
DS110DF1610.
Programmable transmit FIR filter offers control of the
pre-cursor, main tap and post-cursor for transmit
equalization. The fully adaptive receive equalization
(CTLE and DFE) enables longer distance
transmission in lossy copper interconnects and
backplanes with multiple connectors.
A non-disruptive mission mode eye-monitor feature
allows link monitoring internal to the receiver. The
built-in PRBS generator and checker compliment the
internal diagnostic features to complete standalone
BERT measurements. Built-in JTAG enables
manufacturing tests.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
DS110DF1610
FCBGA (196)
15.00 mm × 15.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.

DS110DF1610
DS110DF1610
SNLS472A – JANUARY 2014 – REVISED JUNE 2017
www.ti.com
Table of Contents
1 Features .................................................................. 1
2 Description ............................................................. 1
3 Revision History..................................................... 2
4 Pin Configuration and Functions ......................... 3
5 Specifications......................................................... 8
5.1 Absolute Maximum Ratings (DS110DF1610) .......... 8
5.2 Recommended Operating Conditions....................... 8
5.3 Thermal Characteristics ............................................ 8
5.4 Electrical Characteristics........................................... 9
6 Detailed Description ............................................ 12
6.1 Overview ................................................................. 12
6.2 Functional Block Diagrams ..................................... 12
6.3 Feature Description................................................. 13
6.4 Device Functional Modes........................................ 21
6.5 Programming .......................................................... 22
6.6 Register Maps ......................................................... 23
7 Application and Implementation ........................ 66
7.1 Typical Applications ................................................ 66
7.2 Initialization Setup ................................................... 67
8 Power Supply Recommendations...................... 71
8.1 Power Supply Filtering ............................................ 71
3 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (January 2014) to Revision A
Page
• Changed device status from PRODUCT PREVIEW to PRODUCTION DATA ...................................................................... 1
2 Submit Documentation Feedback
Copyright © 2014–2017, Texas Instruments Incorporated
Product Folder Links: DS110DF1610


Features Product Folder Order Now Technical Doc uments Tools & Software Support & Com munity DS110DF1610 SNLS472A – JANUAR Y 2014 – REVISED JUNE 2017 DS110DF161 0 8.5- to 11.3-Gbps 16-Channel Retimer 1 Features •1 Pin-Compatible Family – DS150DF1610: 12.5 - 15G – DS125DF 1610: 9.8 to 12.5G – DS110DF1610: 8.5 – 11.3G • 4x4 Analog Cross Point S witch for Each Quad • Fully-Adaptive CTLE • Self-Tuning DFE, With Optional Continuous Adaption • On-Chip, AC-co upling on Receive Inputs • Adjustable Transmit VOD • Adjustable 3-Tap Tran smit FIR Filter • Locks to Half/Quart er/Eighth Data Rates For Legacy Support • On-Chip Eye Monitor (EOM), PRBS Ch ecker, PRBS Pattern Generator • Suppo rts IEEE 1149.1 and 1149.6 • Programm able Output Polarity Inversion • Inpu t Signal Detection, CDR Lock Detection • Single 2.5-V ±5% Power Supply • SMBus-Based Register Configuration • Optional EEPROM Configuration • 15-mm × 15-mm, 196-Pin FCBGA Package • Operating Temp Range : –10°C to +85°C Typical Application Diagram 2 Descr.
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