DS110DF410 Channel Retimer Datasheet

DS110DF410 Datasheet, PDF, Equivalent


Part Number

DS110DF410

Description

Low Power Multi-Rate Quad Channel Retimer

Manufacture

etcTI

Total Page 30 Pages
Datasheet
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DS110DF410
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DS110DF410
SNLS397D – OCTOBER 2011 – REVISED APRIL 2015
DS110DF410 Low Power Multi-Rate Quad Channel Retimer
1 Features
1 Each Channel Independently Locks to Data Rates
from 8.5 to 11.3 Gbps and Sub-rates
• Support for Subrates of Divide by 2/4/8
• Fast Lock Operation Based on Protocol-Select
Mode
• Low Latency (~300ps)
• Adaptive Equalization up to 34-dB Boost at 5 GHz
• Adjustable Transmit VOD: 600 to 1300 mVp-p
• Adjustable Transmit De-emphasis to –12 dB
• Typical Power Dissipation (EQ+DFE+CDR+DE):
180 mW/Channel
• Programmable Output Polarity Inversion
• Input Signal Detection, CDR Lock
Detection/Indicator
• On-Chip Eye Monitor (EOM), PRBS Generator
• Single 2.5-V ±5% Power Supply
• SMBus/EEPROM Configuration Modes
• Operating Temperature Range of –40 to 85°C
• WQFN 48-Pin 7-mm × 7-mm Package
• Easy Pin Compatible Upgrade Between Repeater
and Retimers
– DS100RT410 (EQ+CDR+DE): 10.3125 Gbps
– DS100DF410 (EQ+DFE+CDR+DE): 10.3125
Gbps
– DS110RT410 (EQ+CDR+DE): 8.5 - 11.3 Gbps
– DS110DF410 (EQ+DFE+CDR+DE): 8.5 - 11.3
Gbps
– DS125RT410 (EQ+CDR+DE): 9.8 - 12.5 Gbps
– DS125DF410 (EQ+DFE+CDR+DE): 9.8 - 12.5
Gbps
– DS100BR410 (EQ+DE): Up to 10.3125 Gbps
2 Applications
• Front Port SFF 8431 (SFP+) Optical and Direct
Attach Copper
• Backplane Reach Extension, Data Retimer
• Ethernet: 10GbE, 1GbE
• Fibre-Channel, InfiniBand
• Other Propriety Data Rates up to 11.3 Gbps
3 Description
The DS110DF410 is a four channel retimer with
integrated signal conditioning. The device includes a
fully adaptive Continuous-Time Linear Equalizer
(CTLE), self calibrating 5-tap Decision Feedback
Equalizer (DFE), Clock and Data Recovery (CDR),
and transmit De-Emphasis (DE) driver to enable data
transmission over long, lossy and crosstalk-impaired
highspeed serial links to achieve BER < 1×10-15.
Each channel can independently lock to data rates
from 8.5 to 11.3 Gbps, and associated sub rates (div
by 2, 4 and 8) to support a variety of communication
protocols. A 25-MHz crystal oscillator clock is used to
speed up the CDR lock process. This clock is not
used for training the PLL and does not need to be
synchronous with the serial data.
The programmable settings can be applied using the
SMBus (I2C) interface, or they can be loaded via an
external EEPROM. An on-chip eye monitor and a
PRBS generator allow real-time measurement of
high-speed serial data for system bring-up or field
tuning.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
DS110DF410
WQFN (48)
7.00 mm x 7.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
4 Typical Application Diagram
Switch Fabric
ASIC
x4
Back
Plane/
Mid
Plane
1
Line Card
DS110DF410
x4
Optical Modules
x4 10GbE
ASIC
Fibre Channel
InfiniBand
SONET
SFP+ (SFF8431)
Others
x4
DS110DF410
Passive Copper
Clean Signal
Noisy Signal
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.

DS110DF410
DS110DF410
SNLS397D – OCTOBER 2011 – REVISED APRIL 2015
www.ti.com
Table of Contents
1 Features .................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Typical Application Diagram ................................ 1
5 Revision History..................................................... 2
6 Pin Configuration and Functions ......................... 3
7 Specifications......................................................... 6
7.1 Absolute Maximum Ratings ...................................... 6
7.2 ESD Ratings.............................................................. 6
7.3 Recommended Operating Conditions ...................... 6
7.4 Thermal Information .................................................. 6
7.5 Electrical Characteristics........................................... 7
7.6 Typical Characteristics ............................................ 10
8 Detailed Description ............................................ 11
8.1 Overview ................................................................. 11
8.2 Functional Block Diagram ....................................... 11
8.3 Feature Description................................................. 11
8.4 Device Functional Modes........................................ 13
8.5 Programming........................................................... 20
8.6 Register Maps ......................................................... 35
9 Application and Implementation ........................ 51
9.1 Application Information............................................ 51
9.2 Typical Application ................................................. 51
10 Power Supply Recommendations ..................... 53
11 Layout................................................................... 53
11.1 Layout Guidelines ................................................. 53
11.2 Layout Example .................................................... 53
12 Device and Documentation Support ................. 55
12.1 Device Support...................................................... 55
12.2 Documentation Support ........................................ 55
12.3 Trademarks ........................................................... 55
12.4 Electrostatic Discharge Caution ............................ 55
12.5 Glossary ................................................................ 55
13 Mechanical, Packaging, and Orderable
Information ........................................................... 55
5 Revision History
Changes from Revision C (January 2015) to Revision D
Page
• Updated Register 0x2F Values for Table 2 .......................................................................................................................... 16
• Updated descriptions for Address 2 in Table 16 ................................................................................................................. 38
• Added "1: Enabled" and "0: Disabled" to description for Address D in Table 16 ................................................................ 40
• Added "(phase detector charge pump enabled)" and "(frequency detector charge pump enabled)" to description for
Address 1B, Bit 1 and Bit 0, respectively, in Table 16 ........................................................................................................ 41
• Added new content for Address 1F in Table 16 ................................................................................................................... 42
• Updated descriptions for Address 30 in Table 16 ................................................................................................................ 45
• Changed "ADAPT_MODE1" to "RESERVED" for Address 31 Bit 6 Field Name in Table 16.............................................. 45
• Changed "0" to "1" for Address 31 Bit 5 Default Value in Table 16 .................................................................................... 45
Changes from Revision B (May 2013) to Revision C
Page
• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................. 1
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Features Product Folder Sample & Buy Technical Documents Tools & Software Support & Community DS110DF410 SNLS397D – OCTO BER 2011 – REVISED APRIL 2015 DS110DF 410 Low Power Multi-Rate Quad Channel R etimer 1 Features •1 Each Channel In dependently Locks to Data Rates from 8. 5 to 11.3 Gbps and Sub-rates • Suppor t for Subrates of Divide by 2/4/8 • F ast Lock Operation Based on Protocol-Se lect Mode • Low Latency (~300ps) • Adaptive Equalization up to 34-dB Boost at 5 GHz • Adjustable Transmit VOD: 600 to 1300 mVp-p • Adjustable Transm it De-emphasis to –12 dB • Typical Power Dissipation (EQ+DFE+CDR+DE): 180 mW/Channel • Programmable Output Pola rity Inversion • Input Signal Detecti on, CDR Lock Detection/Indicator • On -Chip Eye Monitor (EOM), PRBS Generator • Single 2.5-V ±5% Power Supply • SMBus/EEPROM Configuration Modes • O perating Temperature Range of –40 to 85°C • WQFN 48-Pin 7-mm × 7-mm Pack age • Easy Pin Compatible Upgrade Between Repeater and Retimers – DS100RT410 (EQ+CDR+DE): 10.3125 Gbps –.
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