DS32EV100 Single Equalizer Datasheet

DS32EV100 Datasheet, PDF, Equivalent


Part Number

DS32EV100

Description

Programmable Single Equalizer

Manufacture

etcTI

Total Page 14 Pages
Datasheet
Download DS32EV100 Datasheet


DS32EV100
DS32EV100
www.ti.com
SNLS239D – OCTOBER 2006 – REVISED FEBRUARY 2013
DS32EV100 Programmable Single Equalizer
Check for Samples: DS32EV100
FEATURES
1
2 Equalizes Up to 14 dB loss at 3.2 Gbps
• 8 levels of Programmable Equalization
• Operates up to 3.2 Gbps with 40” FR4 Traces
• 0.12 UI Residual Deterministic Jitter at 3.2
Gbps with 40” FR4 Traces
• Single 2.5V or 3.3V Power Supply
• Supports AC or DC-Coupling with Wide Input
Common-Mode
• Low power Consumption: 100 mW Typ at 2.5V
• Small 3 mm x 4 mm 14-pin WSON Package
• > 8 kV HBM ESD Rating
• -40 to 85°C Operating Temperature Range
DESCRIPTION
The DS32EV100 programmable equalizer provides
compensation for transmission medium losses and
reduces the medium-induced deterministic jitter for
NRZ data channel. The DS32EV100 is optimized for
operation up to 3.2 Gbps for both cables and FR4
traces. The equalizer channel has eight levels of
input equalization that can be programmed by three
control pins.
The equalizer supports both AC and DC-coupled data
paths for long run length data patterns such as
PRBS-31, and balanced codes such as 8b/10b. The
device uses differential current-mode logic (CML)
inputs and outputs. The DS32EV100 is available in a
3 mm x 4 mm 14-pin WSON package. Power is
supplied from either a 2.5V or 3.3V supply.
Simplified Application Diagram
Tx
ASIC/FPGA
High Speed
I/O
Rx
DS32EV100
OUT
IN
Switch Fabric Card
Line Card
Tx
ASIC/FPGA
High Speed
I/O
Rx
DS32EV100
OUT
IN
Backplane/Cable
Sub-system
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2013, Texas Instruments Incorporated

DS32EV100
DS32EV100
SNLS239D – OCTOBER 2006 – REVISED FEBRUARY 2013
Pin Diagram
www.ti.com
NC 1
GND
IN+
IN-
2
3
4
VDD 5
GND
BST_1
6
7
DS32EV100
TOP VIEW
DAP = GND
14 BST_2
13 GND
12 OUT_+
11 OUT_-
10 GND
9 GND
8 BST_0
Figure 1. 14-Pin WSON Package
(3 mm x 4 mm x 0.8 mm, 0.5 mm pitch)
See Package Number NHK0014A
PIN DESCRIPTIONS(1)
Pin Name
Pin #
I/O,
Type
Description
HIGH SPEED DIFFERENTIAL I/O
IN4 I, CML Inverting and non-inverting CML differential inputs to the equalizer. An on-chip 100terminating
IN+ 3
resistor is connected between IN+ and IN. Refer to Figure 5.
OUT
OUT+
11
12
EQUALIZATION CONTROL
O, CML Inverting and non-inverting CML differential outputs from the equalizer. An on-chip 50
terminating resistor connects OUT+ to VDD and OUTto VDD.
BST_2
BST_1
BST_0
14 I, BST_2, BST_1, and BST_0 select the equalizer strength. BST_2 is internally pulled high. BST_1
7 LVCMOS and BST_0 are internally pulled low.
8
POWER
VDD
GND
5
2, 6, 9, 10,
13
Power
Power
VDD = 2.5V ±5% or 3.3V ±10%. VDD pins should be tied to VDD plane through low inductance
path. A 0.01μF bypass capacitor should be connected between each VDD pin to GND planes.
Ground reference. GND should be tied to a solid ground plane through a low impedance path.
DAP
PAD
Power Ground reference. The exposed pad at the center of the package must be connected to ground
plane of the board.
OTHER
NC 1
Reserved. Leave no Connect.
(1) I = Input, O = Output
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
2 Submit Documentation Feedback
Product Folder Links: DS32EV100
Copyright © 2006–2013, Texas Instruments Incorporated


Features DS32EV100 www.ti.com SNLS239D – OCTO BER 2006 – REVISED FEBRUARY 2013 DS3 2EV100 Programmable Single Equalizer Ch eck for Samples: DS32EV100 FEATURES 1 •2 Equalizes Up to 14 dB loss at 3.2 Gbps • 8 levels of Programmable Equal ization • Operates up to 3.2 Gbps wit h 40” FR4 Traces • 0.12 UI Residual Deterministic Jitter at 3.2 Gbps with 40” FR4 Traces • Single 2.5V or 3.3 V Power Supply • Supports AC or DC-Co upling with Wide Input Common-Mode • Low power Consumption: 100 mW Typ at 2. 5V • Small 3 mm x 4 mm 14-pin WSON Pa ckage • > 8 kV HBM ESD Rating • -40 to 85°C Operating Temperature Range DESCRIPTION The DS32EV100 programmable equalizer provides compensation for tra nsmission medium losses and reduces the medium-induced deterministic jitter fo r NRZ data channel. The DS32EV100 is op timized for operation up to 3.2 Gbps fo r both cables and FR4 traces. The equal izer channel has eight levels of input equalization that can be programmed by three control pins. The equalizer supports both AC an.
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