DS32ELX0124 FPGA-Link Deserializer Datasheet

DS32ELX0124 Datasheet, PDF, Equivalent


Part Number

DS32ELX0124

Description

FPGA-Link Deserializer

Manufacture

etcTI

Total Page 30 Pages
Datasheet
Download DS32ELX0124 Datasheet


DS32ELX0124
DS32EL0124, DS32ELX0124
www.ti.com
SNLS284K – MAY 2008 – REVISED APRIL 2013
DS32EL0124 , DS32ELX0124 125 MHz - 312.5 MHz FPGA-Link Deserializer with DDR LVDS
Parallel Interface
Check for Samples: DS32EL0124, DS32ELX0124
FEATURES
1
2 5-bit DDR LVDS Parallel Data Interface
• Programmable Receive Equalization
• Selectable DC-Balance Decoder
• Selectable De-Scrambler
• Remote Sense for Automatic Detection and
Negotiation of Link Status
• No External Receiver Reference Clock
Required
• LVDS Parallel Interface
• Programmable LVDS Output Clock Delay
• Supports Output Data-Valid Signaling
• Supports Keep-Alive Clock Output
• On Chip LC VCOs
• Redundant Serial Input (ELX device only)
• Retimed Serial Output (ELX device only)
• Configurable PLL Loop Bandwidth
• Configurable via SMBus
• Loss of Lock and Error Reporting
• 48-pin WQFN Package with Exposed DAP
APPLICATIONS
• Imaging: Industrial, Medical Security, Printers
• Displays: LED Walls, Commercial
• Video Transport
• Communication Systems
• Test and Measurement
• Industrial Bus
KEY SPECIFICATIONS
• 1.25 to 3.125 Gbps Serial Data Rate
• 125 to 312.5 MHz DDR Parallel Clock
• -40° to +85°C Temperature Range
• > 8 kV ESD (HBM) Protection
• 0.5 UI Minimum Input Jitter Tolerance (1.25
Gbps)
DESCRIPTION
The DS32EL0124/DS32ELX0124 integrates clock
and data recovery modules for high-speed serial
communication over FR-4 printed circuit board
backplanes, balanced cables, and optical fiber. This
easy-to-use chipset integrates advanced signal and
clock conditioning functions, with an FPGA friendly
interface.
The DS32EL0124/DS32ELX0124 deserializes up to
3.125 Gbps of high speed serial data to 5 LVDS
outputs without the need for an external reference
clock. With DC-balance decoding enabled, the
application payload of 2.5 Gbps is deserialized to 4
LVDS outputs.
The DS32EL0124/DS32ELX01214 deserializers
feature a remote sense capability to automatically
signal link status conditions to its companion
DS32EL0421/ELX0421 serializers without requiring
an additional feedback path.
The parallel LVDS interface of these devices reduce
FPGA I/O pins, board trace count and alleviates EMI
issues, when compared to traditional single-ended
wide bus interfaces.
The DS32EL0124/ELX0124 is programmable through
a SMBus interface as well as through control pins.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008–2013, Texas Instruments Incorporated

DS32ELX0124
DS32EL0124, DS32ELX0124
SNLS284K – MAY 2008 – REVISED APRIL 2013
Typical Application
www.ti.com
FPGA
DS32ELX0421
DS32ELX0124
FPGA
5 LVDS
LVDS
Clock
Control
SMBus
Connection Diagrams
3.125 Gbps Data Payload
D0 R0
D1
Redundant
Driver
Redundant Link
Retimed
Output
R1
RT0
PLL Control
PLL Control
5 LVDS
LVDS
Clock
SMBus
Control
VDD33 1
N/C 2
GPIO0 3
GPIO1 4
DC_B 5
RS 6
VDD25 7
N/C 8
N/C 9
N/C 10
GPIO2 11
N/C 12
49 DAP = GND
DS32EL0124
36 VDD33
35 VDD25
34 SMB_CS
33 SCK
32 SDA
31 LOCK
30 RESET
29 N/C
28 VDDPLL
27 LF_CP
26 LF_REF
25 VDD25
Figure 1. WQFN Package
Package Number RHS0048A
2 Submit Documentation Feedback
Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: DS32EL0124 DS32ELX0124


Features DS32EL0124, DS32ELX0124 www.ti.com SNL S284K – MAY 2008 – REVISED APRIL 20 13 DS32EL0124 , DS32ELX0124 125 MHz - 312.5 MHz FPGA-Link Deserializer with D DR LVDS Parallel Interface Check for Sa mples: DS32EL0124, DS32ELX0124 FEATURE S 1 •2 5-bit DDR LVDS Parallel Data I nterface • Programmable Receive Equal ization • Selectable DC-Balance Decod er • Selectable De-Scrambler • Remo te Sense for Automatic Detection and Ne gotiation of Link Status • No Externa l Receiver Reference Clock Required • LVDS Parallel Interface • Programmab le LVDS Output Clock Delay • Supports Output Data-Valid Signaling • Suppor ts Keep-Alive Clock Output • On Chip LC VCOs • Redundant Serial Input (ELX device only) • Retimed Serial Output (ELX device only) • Configurable PLL Loop Bandwidth • Configurable via SM Bus • Loss of Lock and Error Reportin g • 48-pin WQFN Package with Exposed DAP APPLICATIONS • Imaging: Industria l, Medical Security, Printers • Displays: LED Walls, Commercial • Video Transport • Communication Syste.
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