DS90C032QML Line Receiver Datasheet

DS90C032QML Datasheet, PDF, Equivalent


Part Number

DS90C032QML

Description

LVDS Quad CMOS Differential Line Receiver

Manufacture

etcTI

Total Page 19 Pages
Datasheet
Download DS90C032QML Datasheet


DS90C032QML
DS90C032QML
www.ti.com
SNLS203D – MARCH 2006 – REVISED APRIL 2013
DS90C032QML LVDS Quad CMOS Differential Line Receiver
Check for Samples: DS90C032QML
FEATURES
1
2 Single Event Latchup (SEL) Immune 120 MeV-
cm2/mg
• High Impedance LVDS Inputs with Power-Off.
• Accepts Small Swing (330 mV) Differential
Signal Levels
• Low Power Dissipation
• Low Differential Skew
• Low Chip to Chip Skew
• Pin Compatible with DS26C32A
• Compatible with IEEE 1596.3 SCI LVDS
Standard
DESCRIPTION
The DS90C032 is a quad CMOS differential line
receiver designed for applications requiring ultra low
power dissipation and high data rates.
The DS90C032 accepts low voltage differential input
signals and translates them to CMOS (TTL
compatible) output levels. The receiver supports a
TRI-STATE function that may be used to multiplex
outputs. The receiver also supports OPEN Failsafe
and terminated (100) input Failsafe with the addition
of external failsafe biasing. Receiver output will be
HIGH for both Failsafe conditions.
The DS90C032 provides power-off high impedance
LVDS inputs. This feature assures minimal loading
effect on the LVDS bus lines when VCC is not
present.
The DS90C032 and companion line driver
(DS90C031) provide a new alternative to high power
pseudo-ECL devices for high speed point-to-point
interface applications.
Connection Diagrams
Figure 1. Dual-In-Line
See Package Number NAD0016A & NAC0016A
Figure 2. LCCC Package
See Package Number NAJ0020A
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2013, Texas Instruments Incorporated

DS90C032QML
DS90C032QML
SNLS203D – MARCH 2006 – REVISED APRIL 2013
Functional Diagram and Truth Table
Block Diagram
www.ti.com
Receiver
ENABLES
EN EN*
LH
All other combinations of ENABLE inputs
INPUTS
RI+ RI
X
VID 0.1V
VID ≤ −0.1V
OUTPUT
RO
Z
H
L
2 Submit Documentation Feedback
Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: DS90C032QML


Features DS90C032QML www.ti.com SNLS203D – MA RCH 2006 – REVISED APRIL 2013 DS90C0 32QML LVDS Quad CMOS Differential Line Receiver Check for Samples: DS90C032QML FEATURES 1 •2 Single Event Latchup (SEL) Immune 120 MeVcm2/mg • High Imp edance LVDS Inputs with Power-Off. • Accepts Small Swing (330 mV) Differenti al Signal Levels • Low Power Dissipat ion • Low Differential Skew • Low C hip to Chip Skew • Pin Compatible wit h DS26C32A • Compatible with IEEE 159 6.3 SCI LVDS Standard DESCRIPTION The DS90C032 is a quad CMOS differential li ne receiver designed for applications r equiring ultra low power dissipation an d high data rates. The DS90C032 accepts low voltage differential input signals and translates them to CMOS (TTL compa tible) output levels. The receiver supp orts a TRI-STATE function that may be u sed to multiplex outputs. The receiver also supports OPEN Failsafe and termina ted (100Ω) input Failsafe with the ad dition of external failsafe biasing. Receiver output will be HIGH for both Failsafe c.
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