DS90C241

Product Folder Order Now Technical Documents Tools & Software Support & Community DS90C124, DS90C241 SNLS209M – NOVEMBER 2005 – REVISED JANUARY 2017 DS90C241 and DS90C124 5-MHz to 35-MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer 1 Features 1 5-MHz to 35-MHz Clock Embedded and DCBalancing 24:1 and 1:24 Data Transmissions User Defined Pre-Emphasis Driving Ability Through External Resistor on LVDS Outputs and Capable to Drive Up to 10-Meter Shielded Twisted-Pair Cable User-Selectable Clock Edge for Parallel Data on Both Transmitter and Receiver Internal DC Balancing Encode and Decode (Supports AC-Coupling Interface With No External Coding Required) Individual Power-Down Controls for Both Transmitter and Receiver Embedded Clock CDR (Clock and Data Recovery) on Receiver and No External Source of Reference Clock Required All Codes RDL (Random Data Lock) to Support Live-Pluggable Applications LOCK Output Flag to Ensure Data Integrity at Receiver Side Balanced TSETUP and THOLD Between RCLK and RDATA on Receiver Side PTO (Progressive Turnon) LVCMOS Outputs to Reduce EMI and Minimize SSO Effects All LVCMOS Inputs and Control Pins Have Internal Pulldown On-Chip Filters for PLLs on Transmitter and Receiver Temperature Range: –40°C to 105°C Greater Than 8-kV HBM ESD Tolerant Meets AEC-Q100 Compliance Power Supply Range: 3.3 V ± 10% 48-Pin TQFP Package 2 Applications Automotive Central Information Displays Automotive Instrument C...