DS90C383B LVDS Transmitter Datasheet

DS90C383B Datasheet, PDF, Equivalent


Part Number

DS90C383B

Description

Programmable LVDS Transmitter

Manufacture

etcTI

Total Page 18 Pages
Datasheet
Download DS90C383B Datasheet


DS90C383B
DS90C383B
www.ti.com
SNLS177G – APRIL 2004 – REVISED APRIL 2013
Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz
Check for Samples: DS90C383B
FEATURES
1
23 No special start-up sequence required
between clock/data and /PD pins. Input signal
(clock and data) can be applied either before
or after the device is powered
• Support Spread Spectrum Clocking up to
100kHz frequency modulation and deviations
of ±2.5% center spread or -5% down spread
• "Input Clock Detection" feature will pull all
LVDS pairs to logic low when input clock is
missing and when /PD pin is logic high
• 18 to 68 MHz shift clock support
• Best-in-Class Setup and Hold Times on
TxINPUTs
• Tx power consumption < 130 mW (typ) at
65MHz Grayscale
• 40% Less Power Dissipation than BiCMOS
Alternatives
• Tx Power-down mode < 60μW (typ)
• Supports VGA, SVGA, XGA and Dual Pixel
SXGA.
• Narrow bus reduces cable size and cost
• Up to 1.8 Gbps throughput
• Up to 227 Megabytes/sec bandwidth
• 345 mV (typ) swing LVDS devices for low EMI
• PLL requires no external components
• Compatible with TIA/EIA-644 LVDS standard
• Low profile 56-lead TSSOP package
• Improved replacement for:
– SN75LVDS83, DS90C383A
DESCRIPTION
The DS90C383B transmitter converts 28 bits of
CMOS/TTL data into four LVDS (Low Voltage
Differential Signaling) data streams. A phase-locked
transmit clock is transmitted in parallel with the data
streams over a fifth LVDS link. Every cycle of the
transmit clock 28 bits of input data are sampled and
transmitted. At a transmit clock frequency of 65 MHz,
24 bits of RGB data and 3 bits of LCD timing and
control data (FPLINE, FPFRAME, DRDY) are
transmitted at a rate of 455 Mbps per LVDS data
channel. Using a 65 MHz clock, the data throughput
is 227 Mbytes/sec. The DS90C383B transmitter can
be programmed for Rising edge strobe or Falling
edge strobe through a dedicated pin. A Rising edge
or Falling edge strobe transmitter will interoperate
with a Falling edge strobe Receiver (DS90CF386)
without any translation logic.
This chipset is an ideal means to solve EMI and
cable size problems associated with wide, high speed
TTL interfaces.
Block Diagram
Figure 1. DS90C383B
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TRI-STATE is a registered trademark of Texas Instruments.
2
All other trademarks are the property of their respective owners.
3
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2013, Texas Instruments Incorporated

DS90C383B
DS90C383B
SNLS177G – APRIL 2004 – REVISED APRIL 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings (1)
Supply Voltage (VCC)
CMOS/TTL Input Voltage
LVDS Driver Output Voltage
LVDS Output Short Circuit Duration
Junction Temperature
Storage Temperature
Lead Temperature (Soldering, 4 seconds)
Maximum Package Power Dissipation Capacity at 25°C
Package Derating
ESD Rating
TSSOP Package
HBM, 1.5 k, 100 pF
EIAJ, 0, 200 pF
-0.3V to +4 V
-0.3V to (VCC + 0.3) V
-0.3V to (VCC + 0.3) V
Continuous
+150 °C
-65°C to +150 °C
+260 °C
1.63 W
12.5 mW/°C above +25°C
7 kV
500 V
(1) “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be verified. They are not meant to imply
that the device should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.
Recommended Operating Conditions
Supply Voltage (VCC)
Operating Free Air Temperature (TA)
Supply Noise Voltage (VCC)
TxCLKIN frequency
Min Nom Max Unit
3.0 3.3 3.6
V
-10 +25 +70 °C
200 mVPP
18 68 MHz
Electrical Characteristics(1)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ (2)
Max
Unit
CMOS/TTL DC SPECIFICATIONS
VIH High Level Input Voltage
VIL Low Level Input Voltage
VCL Input Clamp Voltage
IIN Input Current
LVDS DC SPECIFICATIONS
ICL = -18 mA
V IN = 0.4V, 2.5V or VCC
V IN = GND
2.0
GND
-10
-0.79
+1.8
0
VCC
0.8
-1.5
+10
V
V
V
μA
μA
VOD
ΔVOD
VOS
ΔVOS
Differential Output Voltage
Change in VOD between
complimentary output states
Offset Voltage (3)
Change in VOS between
complimentary output states
RL = 100
250 345 450
35
1.13 1.25 1.38
35
mV
mV
V
mV
IOS
Output Short Circuit Current
VOUT = 0V, RL = 100
IOZ
Output TRI-STATE® Current
Power Down = 0V,
VOUT = 0V or VCC
-3.5 -5 mA
±1 ±10 μA
(1) Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground
unless otherwise specified (except VOD and ΔVOD).
(2) Typical values are given for VCC = 3.3V and TA = +25°C unless specified otherwise.
(3) VOS previously referred as VCM.
2 Submit Documentation Feedback
Product Folder Links: DS90C383B
Copyright © 2004–2013, Texas Instruments Incorporated


Features DS90C383B www.ti.com SNLS177G – APRI L 2004 – REVISED APRIL 2013 Programm able LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz Check for Sa mples: DS90C383B FEATURES 1 •23 No s pecial start-up sequence required betwe en clock/data and /PD pins. Input signa l (clock and data) can be applied eithe r before or after the device is powered • Support Spread Spectrum Clocking u p to 100kHz frequency modulation and de viations of ±2.5% center spread or -5% down spread • "Input Clock Detection " feature will pull all LVDS pairs to l ogic low when input clock is missing an d when /PD pin is logic high • 18 to 68 MHz shift clock support • Best-in- Class Setup and Hold Times on TxINPUTs • Tx power consumption < 130 mW (typ) at 65MHz Grayscale • 40% Less Power Dissipation than BiCMOS Alternatives Tx Power-down mode < 60μW (typ) • Supports VGA, SVGA, XGA and Dual Pixel SXGA. • Narrow bus reduces cable size and cost • Up to 1.8 Gbps throughput • Up to 227 Megabytes/sec bandwidth • 345 mV (typ) .
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