DS90C385A LVDS Transmitter Datasheet

DS90C385A Datasheet, PDF, Equivalent


Part Number

DS90C385A

Description

+3.3V Programmable LVDS Transmitter

Manufacture

etcTI

Total Page 20 Pages
Datasheet
Download DS90C385A Datasheet


DS90C385A
DS90C385A
www.ti.com
SNLS167K – MARCH 2004 – REVISED APRIL 2013
+3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display Link-87.5 MHz
Check for Samples: DS90C385A
FEATURES
1
23 Pin-to-Pin Compatible to DS90C383,
DS90C383A and DS90C385
• No Special Start-Up Sequence Required
between Clock/Data and /PD Pins. Input
Signals (Clock and Data) can be Applied Either
Before or After the Device is Powered.
• Support Spread Spectrum Clocking up to
100kHz Frequency Modulation and Deviations
of ±2.5% Center Spread or -5% Down Spread
• “Input Clock Detection" Feature Will Pull All
LVDS Pairs to Logic Low When Input Clock is
Missing and When /PD Pin is Logic High
• 18 to 87.5 MHz Shift Clock Support
• Tx Power Consumption < 147 mW (typ) at
87.5MHz Grayscale
• Tx Power-Down Mode < 60 μW (typ)
• Supports VGA, SVGA, XGA, SXGA(Dual Pixel),
SXGA+(Dual Pixel), UXGA(Dual Pixel).
• Narrow Bus Reduces Cable Size and Cost
• Up to 2.45 Gbps Throughput
• Up to 306.25Megabyte/sec Bandwidth
• 345 mV (typ) Swing LVDS Devices for Low EMI
• PLL Requires No External Components
• Compliant to TIA/EIA-644 LVDS standard
• Low Profile 56-lead TSSOP Package
DESCRIPTION
The DS90C385A is a pin to pin compatible
replacement for DS90C383, DS90C383A and
DS90C385. The DS90C385A has additional features
and improvements making it an ideal replacement for
DS90C383, DS90C383A and DS90C385. family of
LVDS Transmitters.
The DS90C385A transmitter converts 28 bits of
LVCMOS/LVTTL data into four LVDS (Low Voltage
Differential Signaling) data streams. A phase-locked
transmit clock is transmitted in parallel with the data
streams over the fifth LVDS link. Every cycle of the
transmit clock 28 bits of input data are sampled and
transmitted. At a transmit clock frequency of 87.5
MHz, 24 bits of RGB data and 3 bits of LCD timing
and control data (FPLINE, FPFRAME, DRDY) are
transmitted at a rate of 612.5Mbps per LVDS data
channel. Using a 87.5 MHz clock, the data throughput
is 306.25Mbytes/sec. This transmitter can be
programmed for Rising edge strobe or Falling edge
strobe through a dedicated pin. A Rising edge or
Falling edge strobe transmitter will interoperate with a
Falling edge strobe FPDLink Receiver without any
translation logic.
This chipset is an ideal means to solve EMI and
cable size problems associated with wide, high-speed
TTL interfaces with added Spread Spectrum Clocking
support.
Block Diagram
Figure 1. DS90C385A
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TRI-STATE is a registered trademark of Texas Instruments.
2
All other trademarks are the property of their respective owners.
3
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2013, Texas Instruments Incorporated

DS90C385A
DS90C385A
SNLS167K – MARCH 2004 – REVISED APRIL 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings(1)
Supply Voltage (VCC)
CMOS/TTL Input Voltage
LVDS Driver Output Voltage
LVDS Output Short Circuit Duration
Junction Temperature
Storage Temperature
Lead Temperature (Soldering, 4 seconds)
Maximum Package Power Dissipation Capacity at 25°C
Package Derating
ESD Rating
Latch Up Tolerance at 25°C
TSSOP Package
HBM, 1.5k, 100pF
EIAJ, 0, 200 pF
-0.3V to +4V
-0.5V to (VCC + 0.3V)
-0.3V to (VCC + 0.3V)
Continuous
+150°C
-65°C to +150°C
+260°C
1.63 W
12.5 mW/°C above +25°C
7kV
500V
±100mA
(1) “Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be ensured. They are not meant to imply
that the device should be operated at these limits. The tables of “Electrical Characteristics" specify conditions for device operation.
Recommended Operating Conditions
Supply Voltage (VCC)
Operating Free Air Temperature (TA)
Supply Noise Voltage (VCC)
TxCLKIN frequency
Min Nom Max Unit
3.0 3.3 3.6
V
-10 +25 +70 °C
200 mVPP
18 87.5 MHz
2 Submit Documentation Feedback
Product Folder Links: DS90C385A
Copyright © 2004–2013, Texas Instruments Incorporated


Features DS90C385A www.ti.com SNLS167K – MARC H 2004 – REVISED APRIL 2013 +3.3V Pr ogrammable LVDS Transmitter 24-Bit Flat Panel Display Link-87.5 MHz Check for Samples: DS90C385A FEATURES 1 •23 Pi n-to-Pin Compatible to DS90C383, DS90C3 83A and DS90C385 • No Special Start-U p Sequence Required between Clock/Data and /PD Pins. Input Signals (Clock and Data) can be Applied Either Before or A fter the Device is Powered. • Support Spread Spectrum Clocking up to 100kHz Frequency Modulation and Deviations of ±2.5% Center Spread or -5% Down Spread • “Input Clock Detection" Feature Will Pull All LVDS Pairs to Logic Low W hen Input Clock is Missing and When /PD Pin is Logic High • 18 to 87.5 MHz S hift Clock Support • Tx Power Consump tion < 147 mW (typ) at 87.5MHz Grayscal e • Tx Power-Down Mode < 60 μW (typ) • Supports VGA, SVGA, XGA, SXGA(Dual Pixel), SXGA+(Dual Pixel), UXGA(Dual P ixel). • Narrow Bus Reduces Cable Siz e and Cost • Up to 2.45 Gbps Throughput • Up to 306.25Megabyte/sec Bandwidth • 345 mV (ty.
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