DS90CF388 Display Interface Datasheet

DS90CF388 Datasheet, PDF, Equivalent


Part Number

DS90CF388

Description

Dual Pixel LVDS Display Interface

Manufacture

etcTI

Total Page 30 Pages
Datasheet
Download DS90CF388 Datasheet


DS90CF388
DS90C387, DS90CF388
www.ti.com
SNLS012H – MAY 2000 – REVISED APRIL 2013
DS90C387, DS90CF388 Dual Pixel LVDS Display Interface (LDI)-SVGA/QXGA
Check for Samples: DS90C387, DS90CF388
FEATURES
1
2 Complies with OpenLDI Specification for
Digital Display Interfaces
• 32.5 to 112/170MHz Clock Support for
DS90C387, 40 to 112MHz Clock Support for
DS90CF388
• Supports SVGA through QXGA Panel
Resolutions
• Drives Long, Low Cost Cables
• Up to 5.38Gbps Bandwidth
• Pre-Emphasis Reduces Cable Loading Effects
• DC Balance Data Transmission Provided by
Transmitter Reduces ISI Distortion
• Cable Deskew of +/1 LVDS Data Bit Time (up
to 80 MHz Clock Rate) of Pair-to-Pair Skew at
Receiver Inputs; Intra-Pair Skew Tolerance of
300ps
• Dual Pixel Architecture Supports Interface to
GUI and Timing Controller; Optional Single
Pixel Transmitter Inputs Support Single Pixel
GUI Interface
• Transmitter Rejects Cycle-to-Cycle Jitter
• 5V Tolerant on Data and Control Input Pins
• Programmable Transmitter Data and Control
Strobe Select (Rising or Falling Edge Strobe)
• Backward Compatible Configuration Select
with FPD-Link
• Optional Second LVDS Clock for Backward
Compatibility w/ FPD-Link
• Support for Two Additional User-Defined
Control Signals in DC Balanced Mode
• Compatible with ANSI/TIA/EIA-644-1995 LVDS
Standard
DESCRIPTION
The DS90C387/DS90CF388 transmitter/receiver pair
is designed to support dual pixel data transmission
between Host and Flat Panel Display up to QXGA
resolutions. The transmitter converts 48 bits (Dual
Pixel 24-bit color) of CMOS/TTL data into 8 LVDS
(Low Voltage Differential Signalling) data streams.
Control signals (VSYNC, HSYNC, DE and two user-
defined signals) are sent during blanking intervals. At
a maximum dual pixel rate of 112MHz, LVDS data
line speed is 672Mbps, providing a total throughput of
5.38Gbps (672 Megabytes per second). Two other
modes are also supported. 24-bit color data (single
pixel) can be clocked into the transmitter at a
maximum rate of 170MHz. In this mode, the
transmitter provides single-to-dual pixel conversion,
and the output LVDS clock rate is 85MHz maximum.
The third mode provides inter-operability with FPD-
Link devices.
The LDI chipset is improved over prior generations of
FPD-Link devices and offers higher bandwidth
support and longer cable drive with three areas of
enhancement. To increase bandwidth, the maximum
pixel clock rate is increased to 112 (170) MHz and 8
serialized LVDS outputs are provided. Cable drive is
enhanced with a user selectable pre-emphasis
feature that provides additional output current during
transitions to counteract cable loading effects. DC
balancing on a cycle-to-cycle basis, is also provided
to reduce ISI (Inter-Symbol Interference). With pre-
emphasis and DC balancing, a low distortion eye-
pattern is provided at the receiver end of the cable. A
cable deskew capability has been added to deskew
long cables of pair-to-pair skew of up to +/1 LVDS
data bit time (up to 80 MHz Clock Rate). These three
enhancements allow cables 5+ meters in length to be
driven. This chipset is an ideal means to solve EMI
and cable size problems for high-resolution flat panel
applications. It provides a reliable interface based on
LVDS technology that delivers the bandwidth needed
for high-resolution panels while maximizing bit times,
and keeping clock rates low to reduce EMI and
shielding requirements. For more details, please refer
to Applications Information.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2000–2013, Texas Instruments Incorporated

DS90CF388
DS90C387, DS90CF388
SNLS012H – MAY 2000 – REVISED APRIL 2013
Transmitter Block Diagram
www.ti.com
Receiver Block Diagram
A0
A1
A2
A3
A4
A5
A6
A7
CLK
DESKEW
PLL
CMOS/TTL OUTPUTS
8 RED1
8 GRN1
8 BLU1
8 RED2
8 GRN2
8 BLU2
FPLINE (HSYNC)
FPFRAME (VSYNC)
DRDY (Data Enable)
POWER DOWN
SHFCLKOUT
(40 to 112 MHz)
Generalized Block Diagram
CMOS/TTL INPUTS
RED1 8
GRN1 8
BLU1 8
RED2 8
GRN2 8
BLU2 8
FPLINE (HSYNC)
FPFRAME (VSYNC)
DRDY (Data Enable)
FPSHIFT IN
(TRANSMIT CLOCK IN)
(40 to 112 MHz)
POWER DOWN
DATA (LVDS)
(280 to 672 Mbit/s
On Each LVDS
Channel)
CLOCK (LVDS)
(40 to 112 MHz)
PLL
DS90C387VJD
CMOS/TTL OUTPUTS
8
RED1
8
GRN1
8
BLU1
8
RED2
8
GRN2
8
BLU2
FPLINE (HSYNC)
FPFRAME (VSYNC)
DRDY (Data Enable)
PLL
DS90CF388VJD
FPSHIFT OUT
(40 to 112 MHz)
POWER DOWN
2 Submit Documentation Feedback
Copyright © 2000–2013, Texas Instruments Incorporated
Product Folder Links: DS90C387 DS90CF388


Features DS90C387, DS90CF388 www.ti.com SNLS012 H – MAY 2000 – REVISED APRIL 2013 DS90C387, DS90CF388 Dual Pixel LVDS Dis play Interface (LDI)-SVGA/QXGA Check fo r Samples: DS90C387, DS90CF388 FEATURE S 1 •2 Complies with OpenLDI Specific ation for Digital Display Interfaces 32.5 to 112/170MHz Clock Support for DS90C387, 40 to 112MHz Clock Support fo r DS90CF388 • Supports SVGA through Q XGA Panel Resolutions • Drives Long, Low Cost Cables • Up to 5.38Gbps Band width • Pre-Emphasis Reduces Cable Lo ading Effects • DC Balance Data Trans mission Provided by Transmitter Reduces ISI Distortion • Cable Deskew of +/ 1 LVDS Data Bit Time (up to 80 MHz Cl ock Rate) of Pair-to-Pair Skew at Recei ver Inputs; Intra-Pair Skew Tolerance o f 300ps • Dual Pixel Architecture Sup ports Interface to GUI and Timing Contr oller; Optional Single Pixel Transmitte r Inputs Support Single Pixel GUI Inter face • Transmitter Rejects Cycle-to-C ycle Jitter • 5V Tolerant on Data and Control Input Pins • Programmable Transmitter Data .
Keywords DS90CF388, datasheet, pdf, etcTI, Dual, Pixel, LVDS, Display, Interface, S90CF388, 90CF388, 0CF388, DS90CF38, DS90CF3, DS90CF, Equivalent, stock, pinout, distributor, price, schematic, inventory, databook, Electronic, Components, Parameters, parts, cross reference, chip, Semiconductor, circuit, Electric, manual, substitute




@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact)