DS90CF363B LVDS Transmitter Datasheet

DS90CF363B Datasheet, PDF, Equivalent


Part Number

DS90CF363B

Description

+3.3V Programmable LVDS Transmitter

Manufacture

etcTI

Total Page 16 Pages
Datasheet
Download DS90CF363B Datasheet


DS90CF363B
DS90CF363B
www.ti.com
SNLS180D – JULY 2004 – REVISED APRIL 2013
+3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display (FPD) Link -65 MHz
Check for Samples: DS90CF363B
FEATURES
1
2 No Special Start-up Sequence Required
between Clock/Data and /PD Pins. Input Signal
(Clock and Data) can be Applied Either Before
or After the Device is Powered.
• Support Spread Spectrum Clocking up to
100KHz Frequency Modulation & Deviations of
±2.5% Center Spread or 5% Down Spread.
• "Input Clock Detection" Feature will Pull all
LVDS Pairs to Logic Low when Input Clock is
Missing and when /PD Pin is Logic High.
• 18 to 68 MHz Shift Clock Support
• Best–in–Class Set & Hold Times on TxINPUTs
• Tx Power Consumption < 130 mW (typ)
@65MHz Grayscale
• 40% Less Power Dissipation than BiCMOS
Alternatives
• Tx Power-Down Mode < 37μW (typ)
• Supports VGA, SVGA, XGA and Dual Pixel
SXGA.
• Narrow Bus Reduces Cable Size and Cost
• Up to 1.3 Gbps Throughput
• Up to 170 Megabytes/sec Bandwidth
• 345 mV (typ) Swing LVDS Devices for Low EMI
• PLL Requires no External Components
• Compatible with TIA/EIA-644 LVDS Standard
• Low Profile 48-lead TSSOP Package
• Improved Replacement for:
– SN75LVDS84, DS90CF363A
DESCRIPTION
The DS90CF363B transmitter converts 21 bits of
CMOS/TTL data into three LVDS (Low Voltage
Differential Signaling) data streams. A phase-locked
transmit clock is transmitted in parallel with the data
streams over a fourth LVDS link. Every cycle of the
transmit clock 21 bits of input data are sampled and
transmitted. At a transmit clock frequency of 65 MHz,
18 bits of RGB data and 3 bits of LCD timing and
control data (FPLINE, FPFRAME, DRDY) are
transmitted at a rate of 455 Mbps per LVDS data
channel. Using a 65 MHz clock, the data throughput
is 170 Mbytes/sec. The DS90CF363B is fixed as a
Falling edge strobe transmitter and will interoperate
with a Falling edge strobe Receiver (DS90CF366)
without any translation logic.
This chipset is an ideal means to solve EMI and
cable size problems associated with wide, high speed
TTL interfaces.
Block Diagram
Figure 1. DS90CF363B
See Package Number DGG0048A
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2013, Texas Instruments Incorporated

DS90CF363B
DS90CF363B
SNLS180D – JULY 2004 – REVISED APRIL 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings (1)(2)
Supply Voltage (VCC)
CMOS/TTL Input Voltage
LVDS Driver Output Voltage
LVDS Output Short Circuit
Duration
Junction Temperature
Storage Temperature
Lead Temperature
(Soldering, 4 sec)
Maximum Package Power Dissipation Capacity @ 25°C
DGG-48 (TSSOP) Package: DS90CF363B
Package Derating:
DS90CF363B
ESD Rating (HBM, 1.5 k, 100 pF)
ESD Rating (EIAJ, 0, 200 pF)
Value
0.3 to +4
0.3 to (VCC + 0.3)
0.3 to (VCC + 0.3)
Continuous
+150
65 to +150
+260
1.98
16 mW/°C above +25°C
7
500
Unit
V
V
V
°C
°C
°C
W
kV
V
(1) Absolute Maximum Ratings are those values beyond which the safety of the device cannot be verified. They are not meant to imply that
the device should be operated at these limits. Electrical Characteristics specify conditions for device operation.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
Recommended Operating Conditions
Supply Voltage (VCC)
Operating Free Air Temperature (TA)
Supply Noise Voltage (VCC)
TxCLKIN frequency
Min Nom
3.0 3.3
10 +25
18
Max
3.6
+70
200
68
Units
V
°C
mVPP
MHz
Electrical Characteristics(1)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
CMOS/TTL DC SPECIFICATIONS
VIH High Level Input Voltage
VIL Low Level Input Voltage
VCL Input Clamp Voltage
IIN Input Current
LVDS DC SPECIFICATIONS
ICL = 18 mA
V IN = 0.4V, 2.5V or VCC
V IN = GND
VOD
ΔVOD
VOS
ΔVOS
Differential Output Voltage
Change in VOD between complimentary
output states
Offset Voltage (3)
Change in VOS between complimentary
output states
RL = 100
IOS Output Short Circuit Current
VOUT = 0V, RL = 100
Min Typ(2) Max
2.0
GND
10
0.79
+1.8
0
VCC
0.8
1.5
+10
250 345
1.13 1.25
3.5
450
35
1.38
35
5
Units
V
V
V
μA
μA
mV
mV
V
mV
mA
(1) Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground
unless otherwise specified (except VOD and ΔVOD ).
(2) Typical values are given for VCC = 3.3V and T A = +25°C unless specified otherwise.
(3) VOS previously referred as VCM.
2 Submit Documentation Feedback
Copyright © 2004–2013, Texas Instruments Incorporated
Product Folder Links: DS90CF363B


Features DS90CF363B www.ti.com SNLS180D – JUL Y 2004 – REVISED APRIL 2013 +3.3V Pr ogrammable LVDS Transmitter 18-Bit Flat Panel Display (FPD) Link -65 MHz Check for Samples: DS90CF363B FEATURES 1 2 No Special Start-up Sequence Require d between Clock/Data and /PD Pins. Inpu t Signal (Clock and Data) can be Applie d Either Before or After the Device is Powered. • Support Spread Spectrum Cl ocking up to 100KHz Frequency Modulatio n & Deviations of ±2.5% Center Spread or −5% Down Spread. • "Input Clock Detection" Feature will Pull all LVDS P airs to Logic Low when Input Clock is M issing and when /PD Pin is Logic High. • 18 to 68 MHz Shift Clock Support Best–in–Class Set & Hold Times on TxINPUTs • Tx Power Consumption < 13 0 mW (typ) @65MHz Grayscale • 40% Les s Power Dissipation than BiCMOS Alterna tives • Tx Power-Down Mode < 37μW (t yp) • Supports VGA, SVGA, XGA and Dua l Pixel SXGA. • Narrow Bus Reduces Ca ble Size and Cost • Up to 1.3 Gbps Throughput • Up to 170 Megabytes/sec Bandwidth • 345 mV (ty.
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