DS90CR216 Strobe LVDS Datasheet

DS90CR216 Datasheet, PDF, Equivalent


Part Number

DS90CR216

Description

+3.3V Rising Edge Data Strobe LVDS

Manufacture

etcTI

Total Page 23 Pages
Datasheet
Download DS90CR216 Datasheet


DS90CR216
DS90CR215, DS90CR216
www.ti.com
SNLS129D – MARCH 1999 – REVISED APRIL 2013
DS90CR215/DS90CR216 +3.3V Rising Edge Data Strobe LVDS
21-Bit Channel Link - 66 MHz
Check for Samples: DS90CR215, DS90CR216
FEATURES
1
2 Single +3.3V Supply
• Chipset (Tx + Rx) Power Consumption <250
mW (typ)
• Power-down Mode (<0.5 mW total)
• Up to 173 Megabytes/sec Bandwidth
• Up to 1.386 Gbps Data Throughput
• Narrow Bus Reduces Cable Size
• 290 mV Swing LVDS Devices for Low EMI
• +1V Common Mode Range (Around +1.2V)
• PLL Requires No External Components
• Low Profile 48-Lead TSSOP Package
• Rising Edge Data Strobe
• Compatible with TIA/EIA-644 LVDS Standard
• ESD Rating > 7 kV
• Operating Temperature: 40°C to +85°C
DESCRIPTION
The DS90CR215 transmitter converts 21 bits of
CMOS/TTL data into three LVDS (Low Voltage
Differential Signaling) data streams. A phase-locked
transmit clock is transmitted in parallel with the data
streams over a fourth LVDS link. Every cycle of the
transmit clock 21 bits of input data are sampled and
transmitted. The DS90CR216 receiver converts the
LVDS data streams back into 21 bits of CMOS/TTL
data. At a transmit clock frequency of 66 MHz, 21 bits
of TTL data are transmitted at a rate of 462 Mbps per
LVDS data channel. Using a 66 MHz clock, the data
throughput is 1.386 Gbit/s (173 Mbytes/s).
The multiplexing of the data lines provides a
substantial cable reduction. Long distance parallel
single-ended buses typically require a ground wire
per active signal (and have very limited noise
rejection capability). Thus, for a 21-bit wide data and
one clock, up to 44 conductors are required. With the
Channel Link chipset as few as 9 conductors (3 data
pairs, 1 clock pair and a minimum of one ground) are
needed. This provides a 80% reduction in required
cable width, which provides a system cost savings,
reduces connector physical size and cost, and
reduces shielding requirements due to the cables'
smaller form factor.
The 21 CMOS/TTL inputs can support a variety of
signal combinations. For example, five 4-bit nibbles
plus 1 control, or two 9-bit (byte + parity) and 3
control.
Block Diagram
Figure 1. DS90CR215
48-Lead TSSOP
See Package Number DGG0048A
Figure 2. DS90CR216 - Improved AC Specifications
See Package Number DGG0048A
Recommended Alternative Device
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1999–2013, Texas Instruments Incorporated

DS90CR216
DS90CR215, DS90CR216
SNLS129D – MARCH 1999 – REVISED APRIL 2013
Connection Diagrams
www.ti.com
Figure 3. DS90CR215
Typical Application
Figure 4. DS90CR216
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
2 Submit Documentation Feedback
Copyright © 1999–2013, Texas Instruments Incorporated
Product Folder Links: DS90CR215 DS90CR216


Features DS90CR215, DS90CR216 www.ti.com SNLS12 9D – MARCH 1999 – REVISED APRIL 201 3 DS90CR215/DS90CR216 +3.3V Rising Edg e Data Strobe LVDS 21-Bit Channel Link - 66 MHz Check for Samples: DS90CR215, DS90CR216 FEATURES 1 •2 Single +3.3V Supply • Chipset (Tx + Rx) Power Con sumption <250 mW (typ) • Power-down M ode (<0.5 mW total) • Up to 173 Megab ytes/sec Bandwidth • Up to 1.386 Gbps Data Throughput • Narrow Bus Reduces Cable Size • 290 mV Swing LVDS Devic es for Low EMI • +1V Common Mode Rang e (Around +1.2V) • PLL Requires No Ex ternal Components • Low Profile 48-Le ad TSSOP Package • Rising Edge Data S trobe • Compatible with TIA/EIA-644 L VDS Standard • ESD Rating > 7 kV • Operating Temperature: −40°C to +85 C DESCRIPTION The DS90CR215 transmitt er converts 21 bits of CMOS/TTL data in to three LVDS (Low Voltage Differential Signaling) data streams. A phase-locke d transmit clock is transmitted in para llel with the data streams over a fourth LVDS link. Every cycle of the transmit clock 21 bits of in.
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