DS90CR217 Strobe LVDS Datasheet

DS90CR217 Datasheet, PDF, Equivalent


Part Number

DS90CR217

Description

+3.3V Rising Edge Data Strobe LVDS

Manufacture

etcTI

Total Page 18 Pages
Datasheet
Download DS90CR217 Datasheet


DS90CR217
DS90CR217
www.ti.com
SNLS226A – OCTOBER 2006 – REVISED FEBRUARY 2013
DS90CR217 +3.3V Rising Edge Data Strobe LVDS 21-Bit Channel Link - 85 MHz
Check for Samples: DS90CR217
FEATURES
1
2 20 to 85 MHz Shift Clock Support
• 50% Duty Cycle on Receiver Output Clock
• Best-in-Class Set & Hold Times on TxINPUTs
• Low Power Consumption
• ±1V Common-Mode Range (Around +1.2V)
• Narrow Bus Reduces Cable Size and Cost
• Up to 1.785 Gbps Throughput
• Up to 223 Mbytes/sec Bandwidth
• 345 mV (typ) Swing LVDS Devices for Low EMI
• PLL Requires No External Components
• Rising Edge Data Strobe
• Compatible with TIA/EIA-644 LVDS Standard
• Low Profile 48-Lead TSSOP Package
DESCRIPTION
The DS90CR217 transmitter converts 21 bits of
CMOS/TTL data into three LVDS (Low Voltage
Differential Signaling) data streams. A phase-locked
transmit clock is transmitted in parallel with the data
streams over a fourth LVDS link. Every cycle of the
transmit clock 21 bits of input data are sampled and
transmitted. At a transmit clock frequency of 85 MHz,
21 bits of TTL data are transmitted at a rate of 595
Mbps per LVDS data channel. Using a 85 MHz clock,
the data throughput is 1.785 Gbit/s (223 Mbytes/sec).
The narrow bus and LVDS signalling of the
DS90CR217 is an ideal means to solve EMI and
cable size problems associated with wide, high-speed
TTL interfaces.
Block Diagram
Figure 1. DS90CR217
See Package Number DGG0048A
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2013, Texas Instruments Incorporated

DS90CR217
DS90CR217
SNLS226A – OCTOBER 2006 – REVISED FEBRUARY 2013
Connection Diagrams
www.ti.com
Typical Application
Figure 2.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
2 Submit Documentation Feedback
Product Folder Links: DS90CR217
Copyright © 2006–2013, Texas Instruments Incorporated


Features DS90CR217 www.ti.com SNLS226A – OCTO BER 2006 – REVISED FEBRUARY 2013 DS9 0CR217 +3.3V Rising Edge Data Strobe LV DS 21-Bit Channel Link - 85 MHz Check f or Samples: DS90CR217 FEATURES 1 •2 20 to 85 MHz Shift Clock Support • 50 % Duty Cycle on Receiver Output Clock Best-in-Class Set & Hold Times on Tx INPUTs • Low Power Consumption • ± 1V Common-Mode Range (Around +1.2V) • Narrow Bus Reduces Cable Size and Cost • Up to 1.785 Gbps Throughput • Up to 223 Mbytes/sec Bandwidth • 345 mV (typ) Swing LVDS Devices for Low EMI PLL Requires No External Components • Rising Edge Data Strobe • Compati ble with TIA/EIA-644 LVDS Standard • Low Profile 48-Lead TSSOP Package DESC RIPTION The DS90CR217 transmitter conve rts 21 bits of CMOS/TTL data into three LVDS (Low Voltage Differential Signali ng) data streams. A phase-locked transm it clock is transmitted in parallel wit h the data streams over a fourth LVDS l ink. Every cycle of the transmit clock 21 bits of input data are sampled and transmitted. At a.
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