DS90CR286AT-Q1

Product Folder Sample & Buy Technical Documents Tools & Software Support & Community DS90CR286AT-Q1 SNLS498A – NOVEMBER 2015 – REVISED DECEMBER 2015 DS90CR286AT-Q1 3.3 V Rising Edge Data Strobe LVDS Receiver 28-Bit Channel Link 66 MHz 1 Features 1 20 to 66 MHz Shift Clock Support 50% Duty Cycle on Receiver Output Clock Best–in–Class Setup & Hold Times on Rx Outputs Rx Power Consumption < 270 mW (typ) at 66 MHz Worst Case Rx Power-down Mode < 200 μW (max) ESD Rating: 4 kV (HBM), 1 kV (CDM) PLL Requires No External Components Compatible with TIA/EIA-644 LVDS Standard Low Profile 56-Pin DGG (TSSOP) Package Operating Temperature: −40°C to +105°C Automotive AEC-Q100 Grade 2 Qualified 2 Applications Video Displays Automotive Infotainment Industrial Printers and Imaging Digital Video Transport Machine Vision OpenLDI-to-RGB Bridge 3 Description The DS90CR286AT-Q1 receiver converts four LVDS (Low Voltage Differential Signaling) data streams back into parallel 28 bits of LVCMOS data. The receiver data outputs strobe on the output clock's rising edge. The receiver LVDS clock operates at rates from 20 to 66 MHz. The DS90CR286AT-Q1 phase-locks to the input LVDS clock, samples the serial bit streams at the LVDS data lines, and converts them into 28-bit parallel output data. At an incoming clock rate of 66 MHz, each LVDS input line is running at a bit rate of 462 Mbps, resulting in a maximum throughput of 1.848 Gbps. The DS90CR286AT-Q1 device is enhan...