DS90CR288A Strobe LVDS Datasheet

DS90CR288A Datasheet, PDF, Equivalent


Part Number

DS90CR288A

Description

+3.3V Rising Edge Data Strobe LVDS

Manufacture

etcTI

Total Page 26 Pages
Datasheet
Download DS90CR288A Datasheet


DS90CR288A
DS90CR287, DS90CR288A
www.ti.com
SNLS056G – OCTOBER 1999 – REVISED MARCH 2013
DS90CR287/DS90CR288A +3.3V Rising Edge Data Strobe LVDS
28-Bit Channel Link - 85MHz
Check for Samples: DS90CR287, DS90CR288A
FEATURES
1
• 20 to 85 MHz Shift Clock Support
• 50% Duty Cycle on Receiver Output Clock
• 2.5 / 0 ns Set & Hold Times on TxINPUTs
• Low Power Consumption
• ±1V Common-Mode Range (around +1.2V)
• Narrow Bus Reduces Cable Size and Cost
• Up to 2.38 Gbps Throughput
• Up to 297.5 Mbytes/sec Bandwidth
• 345 mV (typ) Swing LVDS Devices for Low EMI
• PLL Requires no External Components
• Rising Edge Data Strobe
• Compatible with TIA/EIA-644 LVDS Standard
• Low Profile 56-Lead TSSOP Package
DESCRIPTION
The DS90CR287 transmitter converts 28 bits of
LVCMOS/LVTTL data into four LVDS (Low Voltage
Differential Signaling) data streams. A phase-locked
transmit clock is transmitted in parallel with the data
streams over a fifth LVDS link. Every cycle of the
transmit clock 28 bits of input data are sampled and
transmitted.
The DS90CR288A receiver converts the four LVDS
data streams back into 28 bits of LVCMOS/LVTTL
data. At a transmit clock frequency of 85 MHz, 28 bits
of TTL data are transmitted at a rate of 595 Mbps per
LVDS data channel. Using a 85 MHz clock, the data
throughput is 2.38 Gbit/s (297.5 Mbytes/sec).
This chipset is an ideal means to solve EMI and
cable size problems associated with wide, high-speed
TTL interfaces.
Block Diagram
Figure 1. DS90CR287
See Package Number DGG-56 (TSSOP)
Figure 2. DS90CR288A
See Package Number DGG-56 (TSSOP)
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1999–2013, Texas Instruments Incorporated

DS90CR288A
DS90CR287, DS90CR288A
SNLS056G – OCTOBER 1999 – REVISED MARCH 2013
Pin Diagram for TSSOP Packages
www.ti.com
Figure 3. DS90CR287
Typical Application
Figure 4. DS90CR288A
Figure 5. DS90CR288A
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
2 Submit Documentation Feedback
Copyright © 1999–2013, Texas Instruments Incorporated
Product Folder Links: DS90CR287 DS90CR288A


Features DS90CR287, DS90CR288A www.ti.com SNLS0 56G – OCTOBER 1999 – REVISED MARCH 2013 DS90CR287/DS90CR288A +3.3V Rising Edge Data Strobe LVDS 28-Bit Channel L ink - 85MHz Check for Samples: DS90CR28 7, DS90CR288A FEATURES 1 • 20 to 85 MHz Shift Clock Support • 50% Duty Cy cle on Receiver Output Clock • 2.5 / 0 ns Set & Hold Times on TxINPUTs • L ow Power Consumption • ±1V Common-Mo de Range (around +1.2V) • Narrow Bus Reduces Cable Size and Cost • Up to 2 .38 Gbps Throughput • Up to 297.5 Mby tes/sec Bandwidth • 345 mV (typ) Swin g LVDS Devices for Low EMI • PLL Requ ires no External Components • Rising Edge Data Strobe • Compatible with TI A/EIA-644 LVDS Standard • Low Profile 56-Lead TSSOP Package DESCRIPTION The DS90CR287 transmitter converts 28 bits of LVCMOS/LVTTL data into four LVDS (L ow Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the da ta streams over a fifth LVDS link. Every cycle of the transmit clock 28 bits of input data are.
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